DS16EV5110_0706 NSC [National Semiconductor], DS16EV5110_0706 Datasheet - Page 10

• Manufacturer Part Number: DS16EV5110_0706
• Description: Video Equalizer for DVI, HDMI, and Cat5 Cables
• Manufacturer: NSC [National Semiconductor]

www.national.com
DEVICE STATE AND ENABLE CONTROL
The DS16EV5110 has an Enable feature which provides the
ability to control device power consumption. This feature can
be controlled either via the Enable Pin (EN Pin) or via the
Enable Control Bit which is accessed through the SMBus port
(see Table 1 and Table 3). If Enable is activated, the data
channels and clock channel are placed in the ACTIVE state
and
DS16EV5110 can also be placed in STANDBY mode to save
power. In this mode only the control interface including the
SMBus port as well as the clock channel signal detection cir-
cuit remain active.
CLOCK CHANNEL
The clock channel incorporates a limiting amplifier, a DC off-
set correction, and a TMDS driver (Figure 3).
Register 07[0]
0 : Disable
0 : Disable
1 : Enable
1 : Enable
(SMBus)
all
TABLE 3. Enable and Device State Control
device
(CMOS)
EN Pin
blocks
X
X
1
0
function
Register 03[3]
(EN Control)
(SMBus)
X
X
0
1
as
FIGURE 3. DS16EV5110 Clock Channel
described.
Device State
STANDBY
STANDBY
ACTIVE
ACTIVE
The
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CLOCK CHANNEL SIGNAL DETECT
The DS16EV5110 features a signal detect circuit on the clock
channel. The status of the clock signal can be determined by
either reading the Signal Detect bit (SD) in the SMBus regis-
ters (see Table 1) or by the state of the SD pin. A logic High
indicates the presence of a signal that has exceeded a spec-
ified maximum threshold value (called SD_ON). A logic Low
means that the clock signal has fallen below a minimum
threshold value (called SD_OFF). These values are pro-
grammed via the SMBus (Table 1). If not programmed via the
SMBus, the minimum and maximum thresholds take on the
default values for the minimum and maximum values as indi-
cated in Table 4. The Signal Detect threshold values can be
changed through the SMBus. All threshold values specified
are DC peak-to-peak differential signals (positive signal mi-
nus negative signal) at the input of the device.
TABLE 4. Clock Channel Signal Detect Threshold Values
Bit 1 Bit 0 Minimum Threshold
0
0
1
1
0
1
0
1
Register 06 (mV)
40 (Default)
30
55
45
Maximum Threshold
Register 05 (mV)
70 (Default)
55
90
75
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