DS17285-DS17287 DALLAS [Dallas Semiconductor], DS17285-DS17287 Datasheet - Page 18

• Manufacturer Part Number: DS17285-DS17287
• Description: 3V/5V Real-Time Clock
• Manufacturer: DALLAS [Dallas Semiconductor]

A kickstart sequence occurs when kickstarting is enabled through KSE = 1. While the system is powered
down, the
such a transition is detected, the
time, the kickstart Flag (KF, bank 1, register 04AH) is set, indicating that a kickstart condition has
occurred.
The timing associated with both the wake-up and kickstarting sequences is illustrated in the
Wake-Up/Kickstart Timing Diagram in the Electrical Specifications section of this data sheet. The timing
associated with these functions is divided into five intervals, labeled 1 to 5 on the diagram.
The occurrence of either a kickstart or wake-up condition causes the
described above. During interval 1, if the supply voltage on the DS17285/DS17287 V
the greater of V
active low level. If V
pin is turned off and returns to its high-impedance level. In this event, the
The interrupt flag bit (either WF or KF) associated with the attempted power-on sequence remains set
until cleared by software during a subsequent system power-on.
If V
intervals 2 to 5 in the timing diagram. During interval 2,
active low level, indicating that either WF or KF was set in initiating the power-on. In the diagram
assumed to be pulled up to the V
in response to a successful power-on. The
0.
At the beginning of interval 3, the system processor has begun code execution and clears the interrupt
condition of WF and/or KF by writing 0’s to both of these control bits. As long as no other interrupt
within the DS17285/DS17287 is pending, the
Execution of the application software can proceed. During this time, both the wake-up and kickstart
functions can be used to generate status and interrupts. WF is set in response to a date, hours, minutes,
and seconds match condition. KF is set in response to a low-going transition on
interrupt-enable bit is set (WIE and/or KSE), then the
event. In addition, the other possible interrupt sources within the DS17285/DS17287 can cause
driven low. While system power is applied, the on-chip logic always attempts to drive the
in response to the enabled kickstart or wake-up condition. This is true even if
inactive as the result of power being applied by some means other than wake-up or kickstart.
The system can be powered down under software control by setting the PAB bit to a logic 1. This causes
the open-drain
the timing diagram. As V
V
the both the WF and KF flags should be cleared and WIE and/or KSE should be enabled prior to setting
the PAB bit.
CC
CC
goes below V
is applied within the timeout period, then the system power-on sequence continue as shown in
KS
input pin is monitored for a low-going transition of minimum pulse width t
PWR
BAT
PF
or V
. If the system is to be again powered on in response to a wake-up or kickstart, then
pin to be placed in a high-impedance state, as shown at the beginning of interval 4 in
CC
does not rise above the greater of V
PF
CC
before the power-on timeout period (t
voltage decays, the
PWR
BAUX
line is pulled low, as it is for a wake-up condition. Also at this
supply. Also at this time, the PAB bit is automatically cleared to 0
PWR
line remains active as long as the PAB remains cleared to
IRQ
IRQ
18 of 38
output pin is placed in a high-impedance state when
IRQ
line is taken inactive once these bits are reset.
line is driven active low in response to enabled
PWR
BAT
or V
remains active and
POTO
PF
) expires, then PWR remains at the
in this time, then the
PWR
IRQ
pin also remains tri-stated.
pin to be driven low, as
PWR
KS
IRQ
CC
. If the associated
KSPW
was previously
PWR
pin rises above
is driven to its
PWR
. When
pin active
IRQ
output
KS
to be
is