DS90UR124IVS NSC [National Semiconductor], DS90UR124IVS Datasheet - Page 13

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DS90UR124IVS

Manufacturer Part Number
DS90UR124IVS
Description
5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
Manufacturer
NSC [National Semiconductor]
Datasheet

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DS90UR241 SERIALIZER PIN DESCRIPTIONS
22
21
16
17
14
15
30
31
7
6
42
43
24
4-1,
48-44,
41-32,
29-25
10
9
18
13
23
11
12
5
8
20
19
DS90UR124 DESERIALIZER PIN DESCRIPTIONS
51
52
59
58
57
56
32
31
Pin #
Pin Descriptions
VDDDR
VSSDR
VDDPT0
VSSPT0
VDDPT1
VSSPT1
VDDT
VSST
VDDL
VSSL
VDDIT
VSSIT
RESVRD
D
TCLK
TPWDNB
DEN
RESRVD
PRE
TRFB
RAOFF
RESVRD
RESVRD
D
D
VDDIR
VSSIR
VDDPR0
VSSPR0
VDDPR1
VSSPR1
VDDR1
VSSR1
Pin Name
IN
OUT+
OUT−
[23:0]
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
CMOS_I
CMOS_I
CMOS_I
CMOS_I
CMOS_I
CMOS_I
CMOS_I
CMOS_I
CMOS_I
CMOS_I
CMOS_I
LVDS_O
LVDS_O
VDD
GND
VDD
GND
VDD
GND
VDD
GND
I/O/PWR
Analog Voltage supply, LVDS Output POWER
Analog Ground, LVDS Output GROUND
Analog Voltage supply, VCO POWER
Analog Ground, VCO GROUND
Analog Voltage supply, PLL POWER
Analog Ground, PLL GROUND
Digital Voltage supply, Tx serializer POWER
Digital Ground, Tx serializer GROUND
Digital Voltage supply, Tx Logic POWER
Digital Ground, Tx Logic GROUND
Digital Voltage supply, Tx INPUT POWER
Digital Ground, Tx Input GROUND
RESeRVeD MUST tie LOW
Transmitter Data INputs
Transmitter reference CLocK.
Used to strobe data at the D
Transmitter PoWer DowN Bar (ACTIVE L).
TPWDNB = L; Disabled, D
TPWDNB = H; Enabled
Data ENable (ACTIVE H)
DEN = L; Disabled, D
DEN = H; Enabled
RESeRVeD - MUST tie Low
PRE-emphasis select pin.
PRE = (R
PRE = H or floating; pre-emphasis is disabled
Transmitter Rising/Falling Bat Clock Edge Select
TRFB = L; falling edge
TRFB = H; rising edge
Additional RAndomizer OFF. (ACTIVE H)
RAOFF = L; (default) Additional randomization ON
RAOFF = H; backwards compatible with DS90C124
RESeRVeD MUST tie LOW
RESeRVeD MUST tie LOW
Transmitter LVDS true (+) OUTput
Transmitter LVDS inverted (-) OUTput
Analog LVDS Voltage supply, POWER
Analog LVDS GrouND
Analog Voltage supply, PLL POWER
Analog Ground, PLL GROUND
Analog Voltage supply, PLL VCO POWER
Analog Ground, PLL VCO GROUND
Digital Voltage supply, LOGIC POWER
Digital Ground, Logic GROUND
PRE
≥ 6 kΩ); I
OUT
13
max
(+/-) are TRI-STATED, PLL still operational
OUT
= [(1.2/R) x 20 x 2], R
IN
inputs and to drive the transmitter PLL
(+/-) are TRI-STATED stand-by mode, PLL is shutdown
Description
min
= 6 kΩ
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