DS1743P DALLAS [Dallas Semiconductor], DS1743P Datasheet - Page 4

• Manufacturer Part Number: DS1743P
• Description: Y2KC Nonvolatile Timekeeping RAM
• Manufacturer: DALLAS [Dallas Semiconductor]

CLOCK ACCURACY (DIP MODULE)
The DS1743 is guaranteed to keep time accuracy to within 1 minute per month at 25 C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require
additional For this reason, methods of field clock calibration are not available and not necessary. Clock
accuracy is also effected by the electrical environment and caution should be taken to place the RTC in the
lowest level EMI section of the PCB layout. For additional information please see application note 58.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1743 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within 1.53 minutes per month (35 ppm) at 25°C. Clock
accuracy is also effected by the electrical environment and caution should be taken to place the RTC in the
lowest level EMI section of the PCB layout. For additional information please see application note 58.
DS1743 REGISTER MAP Table 2
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1743 is in the read mode whenever
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within t
stable, providing that the
states are not met, valid data will be available at the latter of chip enable access (t
access time (t
outputs are activated before t
inputs are changed while
(t
W = WRITE BIT
OH
ADDRESS
OSC
) but will then go indeterminate until the next address access.
1FFD
1FFA
1FFE
1FFC
1FFB
1FF9
1FF8
1FFF
= STOP BIT
CEA
OSC
BF
B
W
X
X
X
X
7
). The state of the data input/output pins (DQ) is controlled by
FT
B
X
X
X
R
6
10 Year
CE
CE
10 SECONDS
10 MINUTES
, and
, and
AA
10 CENTURY
, the data lines are driven to an intermediate state until t
B
X
X
10 HOUR
5
10 Date
OE
OE
R = READ BIT
X = SEE NOTE BELOW
10 Mo
access times and states are satisfied. If
remain valid, output data will remain valid for output data hold time
B
DATA
X
4
OE
(output enable) is low,
B
X
3
4 of 17
CENTURY
MINUTES
SECONDS
MONTH
B
HOUR
YEAR
DATE
2
DAY
B
1
B
FT = FREQUENCY TEST
BF = BATTERY FLAG
0
WE
AA
(write enable) is high, and
after the last address input is
CE
FUNCTION/RANGE
CONTROL
SECONDS
MINUTES
MONTH
, or
HOUR
YEAR
DATE
DAY
CEA
CE
OE
) or at output enable
AA
, and
access times and
. If the address
DS1743/DS1743P
OE
01-31
01-07
00-23
00-59
00-39
00-99
01-12
00-59
. If the
CE