DS2756E+TR MAXIM [Maxim Integrated Products], DS2756E+TR Datasheet - Page 18

• Manufacturer Part Number: DS2756E+TR
• Description: High-Accuracy Battery Fuel Gauge with Programmable Suspend Mode
• Manufacturer: MAXIM [Maxim Integrated Products]

Table 3. SUMMARY OF SUSPEND MODES
The desired default value should be set in bit 6 and bit 7 of address 31h. The factory default is 00b.
PMOD—Power Mode Enable. A value of 1 in this bit enables the DS2756 to enter Sleep mode or Suspend mode.
A value of 0 disables the DS2756 from entering the Sleep or Suspend mode. When PMOD is 0, only Active mode
operation is allowed. The desired default value must be set in bit 5 of address 31h. The factory default is 0.
RNAOP—Read Net Address Opcode. A value of 0 in this bit sets the opcode for the Read Net Address command
to 33h, while a 1 sets the opcode to 39h. This bit is read-only. The desired default value should be set in bit 4 of
address 31h. The factory default is 0.
UVEN—Undervoltage Sleep Enable. A value of 1 in UVEN along with a value of 1 in PMOD enables the DS2756 to
enter Sleep mode when the voltage on V
of 0 disables the DS2756 from entering the Sleep mode due to undervoltage events. The desired default value
must be set in bit 3 of address 31h. The factory default is 0.
IOS—Interrupt output select. IOS set to a 1 selects the DQ alarm interrupt signaling method for the Alarm
Comparator interrupt. IOS cleared to 0 selects the PIO alarm interrupt signaling method. The IE bit must be set and
PIE bits cleared to signal an Alarm Comparator interrupt using either method. The desired default value must be
set in bit 2 of address 31h. The factory default is 0.
OBEN—Offset Blanking Enable. A value of 1 in this bit location enables the offset blanking function described in
the Current Accumulation section. If set to 0, the offset blanking function is disabled. The desired default value
must be set in bit 1 of address 31h. The factory default is 0.
OVD—Overdrive Timing Enable. A value of 1 in this bit location enables the Overdrive 1-Wire timings. If set to 0,
the Regular mode timings are enabled. The desired bit value must be written to bit 1 of address 31h, (an EEPROM
block 0 location), then recalled before any change to the 1-Wire speed becomes effective. A power-on reset forces
a recall of settings from EEPROM block 0. The factory default in bit 1 of address 31h is 0 (Standard 1-Wire timing).
X—Reserved Bits.
EEPROM REGISTER
The format of the EEPROM Register is shown in Figure 16. The function of each bit is described in detail in the
following paragraphs.
Figure 16. EEPROM Register Format
PIE1
0
0
1
1
PIE0
0
1
0
1
EEC
bit 7
SAMPLE RATE WHILE IN
Suspend mode disabled
LOCK
SUSPEND MODE
bit 6
2.0Hz
1.0Hz
0.5Hz
bit 5
X
IN
drops below undervoltage threshold V
bit 4
Address 07h
X
18 of 26
bit 3
X
AVERAGE IDD WHILE IN SUSPEND MODE
(1000ms × I
(2000ms × I
(500ms × I
bit 2
BL2
Suspend mode disabled
SUSPEND
SUSPEND
SUSPEND
UV
1090ms
2090ms
590ms
bit 1
BL1
for t
) + (90ms × I
) + (90ms × I
) + (90ms × I
UVD
(cell depletion). A value
bit 0
BL0
ACTIVE
ACTIVE
ACTIVE
)
)
)