DS92CK16_06 NSC [National Semiconductor], DS92CK16_06 Datasheet

DS92CK16_06

Manufacturer Part Number

DS92CK16_06

Description

3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

Manufacturer

NSC [National Semiconductor]

Datasheet

1.DS92CK16_06.pdf (12 pages)

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DS92CK16

3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver

General Description

The DS92CK16 1 to 6 Clock Buffer/Bus Transceiver is a one

to six CMOS differential clock distribution device utilizing Bus

Low Voltage Differential Signaling (BLVDS) technology. This

clock distribution device is designed for applications requir-

ing ultra low power dissipation, low noise, and high data

rates. The BLVDS side is a transceiver with a separate

channel acting as a return/source clock.

The DS92CK16 accepts LVDS (300 mV typical) differential

input levels, and translates them to 3V CMOS output levels.

An output enable pin OE , when high, forces all CLK

high.

The device can be used as a source synchronous driver. The

selection of the source driving is controlled by the CrdCLK

and DE pins. This device can be the master clock, driving the

inputs of other clock I/O pins in a multipoint environment.

Easy master/slave clock selection is achieved along a back-

plane.

Function Diagram and Truth Table

L = Low Logic State

H = High Logic State

X = Irrelevant

Z = TRI-STATE

TRI-STATE

OE DE

is a registered trademark of National Semiconductor Corporation.

CrdCLK

Receive Mode Truth Table

INPUT

(CLKI/O+)–(CLKI/O−)

VID≤ −0.07V

VID≥ 0.07V

DS101082

OUTPUT

CLK

OUT

pins

Features

n Master/Slave clock selection in a backplane application

n 125 MHz operation (typical)

n 100 ps duty cycle distortion (typical)

n 50 ps channel to channel skew (typical)

n 3.3V power supply design

n Glitch-free power on at CLKI/O pins

n Low Power design (20 mA

n Accepts small swing (300 mV typical) differential signal

n Industrial temperature operating range (-40˚C to +85˚C)

n Available in 24-pin TSSOP Packaging

levels

DE CrdCLK

INPUT

Driver Mode Truth Table

CLK/I/O+

3.3V static)

10108201

OUTPUT

CLKI/O−

www.national.com

April 2006

CLK

OUT

Related parts for DS92CK16_06

DS92CK16_06 Summary of contents

Page 1

DS92CK16 3V BLVDS Clock Buffer/Bus Transceiver General Description The DS92CK16 Clock Buffer/Bus Transceiver is a one to six CMOS differential clock distribution device utilizing Bus Low Voltage Differential Signaling (BLVDS) technology. This clock distribution ...

Page 2

Connection Diagram TSSOP Package Pin Descriptions Pin Name Pin # CLKI/O+ 6 CLKI/O− CLK 13, 15, 17, 19, 21, 23 OUT CrdCLK 16, 20 GND 1, 12, 14, 18, 22 ...

Page 3

Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Enable Input Voltage (DE, OE, CrdCLK ) IN Voltage (CLK ) OUT ± Voltage ...

Page 4

DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 3, 4). Symbol Parameter I No Load Supply Current 0V, CC Outputs Enabled, No VID CrdCLK Applied CLKI/O ( CLK I No ...

Page 5

Switching Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 7, 8). Symbol Parameter DIFFERENTIAL RECEIVER CHARACTERISTICS t Differential Propagation Delay High to Low. CLKI/O to PHLDR CLK OUT t Differential Propagation Delay Low to High. CLKI/O ...

Page 6

Switching Characteristics Note 10 the difference in receiver propagation delay (|t SK1R V . The propagation delay specification is a device to device worst case over process, voltage and temperature. CC Note 11 the difference in ...

Page 7

Parameter Measurement Information FIGURE 4. Output Enable (OE) Delay Waveforms FIGURE 6. Driver Propagation Delay Test Circuit (Continued) FIGURE 5. Differential Driver DC Test 10108208 7 10108206 10108207 www.national.com ...

Page 8

Parameter Measurement Information FIGURE 7. Driver Propagation Delay and Transition Time Waveforms FIGURE 8. CrdCLK FIGURE 9. CrdCLK www.national.com (Continued) 10108210 Propagation Delay Time Test Circuit IN 10108211 Propagation Delay Time Waveforms IN 8 10108209 ...

Page 9

Parameter Measurement Information (Continued) FIGURE 10. Driver TRI-STATE Test Circuit FIGURE 11. Driver TRI-STATE Waveforms 9 10108212 10108213 www.national.com ...

Page 10

Applications Information General application guidelines and hints for BLVDS/LVDS transceivers, drivers and receivers may be found in the following application notes: LVDS Owner’s Manual (lit #550062-001), AN805, AN807, AN808, AN903, AN905, AN916, AN971, AN977 . BLVDS drivers and receivers are ...

Page 11

Applications Information Surface mount resistors are best. PROBING BLVDS TRANSMISSION LINES > Always use high impedance ( 100kΩ), low capacitance < ( 2pF) scope probes with a wide bandwidth (1GHz) scope. Improper probing will give deceiving results. ...

Page 12

Physical Dimensions inches (millimeters) unless otherwise noted National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and ...

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