DS1855 DALLAS [Dallas Semiconductor], DS1855 Datasheet - Page 15

• Manufacturer Part Number: DS1855
• Description: Dual Nonvolatile Digital Potentiometer and Secure Memory
• Manufacturer: DALLAS [Dallas Semiconductor]

NOTES:
1. All voltages are referenced to ground.
2. I
3. I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if V
4. A fast mode-device can be used in a standard mode system, but the requirement t
5. After this period, the first clock pulse is generated.
6. The maximum t
7. C
8. EEPROM write begins after a STOP condition occurs.
9. Absolute linearity is used to measure expected wiper voltage as determined by wiper position.
10. Relative linearity is used to determine the change of wiper voltage between two adjacent wiper
11. I
12. Maximum I
logic levels. Appropriate logic levels specify that logic inputs are within a 0.5V of ground or V
the corresponding inactive state.
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line t
SCL signal.
positions.
STBY
CC
B
– Total capacitance of one bus line in picofarads, timing referenced to (0.9)(V
specified with SDA pin open.
specified with for V
CC
is dependent on clock rates.
HD:DAT
has only to be met if the device does not stretch the LOW period (t
RMAX
CC
= 3.0V and 5.0V, and control port logic pins are driven to the appropriate
+ t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line is released.
15 of 20
CC
is switched off.
CC
SU:DAT
) and (0.1)(V
> 250ns must
LOW
) of the
CC
CC
).
for