ak8825 AKM Semiconductor, Inc., ak8825 Datasheet - Page 32

• Manufacturer Part Number: ak8825
• Description: Hd/sd Multi Format Video Encoder With 3ch Dac
• Manufacturer: AKM Semiconductor, Inc.

■ Clock
D1 = 480i/576i(525i/625i), D2 = 480p/576p (525p/625p), D3 = 1080i (1125i), D4 = 720p (750p)
In case of switching clock, PLLPDN-bit of Powerdown Mode Register (R/W) [Sub Address 0x06] should be “0”.
■ Internal PLL
Powerdown Mode Register
Sub Address 0x06
■ Reset
(1) Component Video Encoder Block and High Speed DAC Block, and Serial Interface Block are reset with making
(2) Composite Video Encoder Block.
DAC Control Register
Sub Address 0x0D
After Reset all register values become default value, and Video DAC output pins become Hi-z.
Rev-E-00
Input Clock is determined by output signal. The relation between input Clock and the output signal is defined as following table.
Input Clock
Input Clock to CLKIN pin
DAC operation clock rate
Internal PLL status
AK8825 has x2 PLL.
In case of Component Video Encoder mode, PLL should be on.
In time to switch clock rate, PLLPDN-bit should be “0”.
Address 0x0D] with clock input to CLKIN-pin. It should be keep DTSTN-bit = “0” at least 100 clock count.
Reserved
Reserved
PLLPDN
PDN-pin = Low. It is not necessary to input clock to CLKIN pin.
Composite Video Encoder Block is reset under the condition of DTRSTN-bit =”0” of DAC Control Register(R/W) [Sub
bit 7
bit 7
0
1
PLL is Power Down
PLL is working.
Set PLLPDN=1, in case of Component Video Encoder mode.
Reserved
Reserved
bit 6
bit 6
< HD Block >
Composite Video Encoder
Reserved
OLVL
bit 5
bit 5
NTSC/PAL
27MHz
27MHz
mode
OFF
Reserved
DTRSTN
bit 4
bit 4
Function
32
Component Video Encoder
D1, D2
27MHz
54MHz
ON
CVBSSEL
Reserved
bit 3
bit 3
mode
74.25MHz
148.5MHz
D3, D4
DAC3EN
PLLPDN
ON
bit 2
bit 2
54MHz (max)
Clock to CLKIN pin
OFF
High Speed Video DAC mode
DAC2EN
SLPEN1
bit 1
bit 1
default Value 0x00
Default Value 0x00
DAC1EN
SLPEN0
bit 0
bit 0
2008/03
[AK8825]