DS99R124QSQ NSC [National Semiconductor], DS99R124QSQ Datasheet
DS99R124QSQ
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DS99R124QSQ Summary of contents
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MHz 18-bit Color FPD-Link II to FPD-Link Converter General Description The DS99R124Q converts FPD-Link II to FPD-Link. It trans- lates a high-speed serialized interface with an embedded clock over a single pair (FPD-Link II) to three LVDS ...
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DS99R124Q Pin Diagram Pin Descriptions Pin Name Pin # I/O, Type FPD-Link II Input Interface RIN LVDS RIN LVDS CMF 42 I, Analog FPD-Link Output Interface TxOUT[2:0]+ 19, 21 LVDS TxOUT[2:0]- 20, 22, 24 ...
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Pin Name Pin # I/O, Type LVCMOS Outputs OS[2:0] 10, 11 LVMOS LOCK 27 O, LVMOS Control and Configuration PDB 1 I, LVCMOS w/ pull-down VODSEL 33 I, LVCMOS w/ pull-down OEN 34 I, LVCMOS w/ pull-down OSS_SEL ...
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... LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch DS99R124QSQ 48–pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch DS99R124QSQX 48–pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch Note: Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies. Reliability qualification is compliant with the requirements and temperature grades defined in the AEC Q100 standard ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage – V (1.8V) DDn Supply Voltage – V (3.3V) DDTX Supply Voltage – V DDIO LVCMOS I/O ...
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Symbol Parameter V High Level Output Voltage OH V Low Level Output Voltage OL I Output Short Circuit Current OS I TRI-STATE ® Output Current OZ 1.8 V I/O LVCMOS DC SPECIFICATIONS – High Level Input Voltage IH ...
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Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter FPD-Link II t Lock Time DDLT (Note 5) t Input Jitter Tolerance DJIT FPD-Link Output t Low to High Transition Time TLHT t High to Low ...
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Recommended Timing for the Serial Control Bus Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter f SCL Clock Frequency SCL t SCL Low Period LOW t SCL High Period HIGH t Hold time for a start ...
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Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond ...
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FIGURE 3. FPD-Link & LVCMOS Powerdown Delay FIGURE 4. FPD-Link Outputs Enable Delay FIGURE 5. Deserializer PLL Lock Times 10 30105288 30105289 30105214 ...
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FIGURE 6. FPD-Link (LVDS) Single-ended and Differential Waveforms FIGURE 7. FPD-Link Transmitter Pulse Positions FIGURE 8. Receiver Input Jitter Tolerance 11 30105206 30105217 30105216 www.national.com ...
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Typical Performance Characteristics FIGURE 11. Typical Input Jitter Tolerance Curve at 43 MHz www.national.com FIGURE 9. BIST PASS Waveform FIGURE 10. Serial Control Bus Timing Diagram 12 30105252 30105236 30105291 ...
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FIGURE 12. Typical Total IDD Current (1.8V Supply Function of PCLK FIGURE 13. Typical IDDTX Current (3.3V Supply function of PCLK 13 30105292 30105293 www.national.com ...
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Functional Description The DS99R124Q receives 24-bits of data over a single serial FPD-Link II pair operating at 140Mbps to 1.2Gbps. The serial stream also contains an embedded clock, and the DC-bal- ance information which enhances signal quality and supports AC ...
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INPUTS PDB OEN OSS_SEL LVCMOS 1.8V / 3.3V VDDIO Operation The LVCMOS inputs and outputs can operate with 1 3.3 V levels ...
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TABLE 3. SSCG Configuration (LFMODE = L) — Des Output SSC[2:0] Inputs LFMODE = L ( MHz) SSC2 SSC1 TABLE 4. SSCG Configuration (LFMODE = H) ...
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FIGURE 17. BIST Mode Flow Diagram Sample BIST Sequence SeeFigure 17 for the BIST mode flow diagram. Step 1: For the DS99R421 FPD-Link II Ser BIST Mode is en- abled via the BISTEN pin. For the DS90UR241 Ser, BIST mode ...
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Serial Bus Control — Optional The DS99R124 may also be configured by the use of a serial control bus that is I2C protocol compatible. By default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/ ...
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TABLE 6. DS99R124Q — Serial Bus Control Registers ADD ADD Register Name Bit(s) (dec) (hex Des Config 3 Slave Des Features ...
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ADD ADD Register Name Bit(s) (dec) (hex Des Features 2 7:5 2:0 www.national.com R/W Defa Function ult (bin) R/W 000 EQ Gain 4 R Enable 3 R/W 0 Reserved R/W 000 SSC 20 Description 000: ~1.625 ...
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Applications Information DISPLAY APPLICATION The DS99R124Q, in conjunction with the DS99R421Q or DS90UR241Q, is intended for interfacing between a host (graphics processor) and a Display. It supports an 18-bit color depth (RGB666) and up to WVGA display formats ...
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Power Up Requirements and PDB Pin The VDD ( and V DDn DDTX DDIO faster than 1.5 ms with a monotonic rise. Supplies may power up in any order, however device operation should be initiated only after all ...
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Physical Dimensions inches (millimeters) unless otherwise noted 48–pin LLP Package (7 7 0.8 mm, 0.5 mm pitch) NS Package Number SQA48A 23 www.national.com ...
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For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs ...