ip1718lf ETC-unknow, ip1718lf Datasheet - Page 7

no-image

ip1718lf

Manufacturer Part Number
ip1718lf
Description
18-port 10/100mbps Smart Switch Controller
Manufacturer
ETC-unknow
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IP1718LF
Manufacturer:
ICPLUS
Quantity:
2 839
Pin description (continued)
Copyright © 2003, IC Plus Corp.
MII/Reverse MII
95
94, 93, 92, 91
84
88, 87, 86, 85
90
89
111
110,109,108,1
07
98
104,103,100,9
9
106
105
112
13
14
Miscellaneous
70
71
72
97
75
76
78
79
77
74
Pin No.
M1TXEN
M1TXD[3:0]
M1RXDV
M1RXD[3:0]
M1TXC
M1RXC
M2TXEN
M2TXD[3:0]
M2RXDV
M2RXD[3:0]
M2TXC
M2RXC
M2COL
MDC
MDIO
X1/OSCI
X2
RESETB
CLK25M
SCL
SDA
SCPUC
SCPUIO
INTB
TEST
Label
I/O,PU Serial EEPROM data
O, PU Serial EEPROM clock output
O, PU Interrupt output. Active low.
O, PD Test mode control.
Type
I, PU
I/O,
I/O
I/O
I/O
I/O
I/O
I/O
PU
O
O
O
O
O
O
O
I
I
I
I
I
I
1st MII (port 17) transmit enable
1st MII (port 17) transmit data output
1st MII (port 17) receive valid
1st MII (port 17) receive data input
1st MII (port 17) transmit clock. Input for normal (MAC
mode) MII. Output for reverse (PHY mode) MII
1st MII (port 17) receive clock. Input for normal (MAC
mode) MII. Output for reverse (PHY mode) MII.
2nd MII (port 18) transmit enable
2nd MII (port 18) transmit data output
2nd MII (port 18) receive valid
2nd MII (port 18) receive data input
2nd MII (port 18) transmit clock. Input for normal (MAC
mode) MII. Output for reverse (PHY mode) MII
2nd MII (port 18) receive clock. Input for normal (MAC
mode) MII. Output for reverse (PHY mode) MII.
2nd MII (port 18) collision input. Input for normal MII
Output for reverse MII
Clock for serial management bus. It’s recommended to
add a 30pf capacitor to ground for noise filetrring.
I/O data for serial manment bus. It’s recommended to
add a 4.7K pull up resistor connecting to VDD and a
30pf capacitor connecting to ground.
Crystal/ Oscillator 25MHz input
Crystal output
System reset (low active). Should be kept at “low” for at
least 10 microseconds.
This output pin is 25MHz clock signal which is the
counterpart of the clock generated by the X’tal placed
on X1 & X2.
Serial CPU access clock input. Please see the section
of “Programming the Internal Register” for the usage of
SCPUC and SCPUIO.
Serial CPU data
7/33
Description
Preliminary Data Sheet
IP1718 LF-DS-R05
IP1718 LF
January 27, 2005

Related parts for ip1718lf