A25L05PMF-50 AMICC [AMIC Technology], A25L05PMF-50 Datasheet
A25L05PMF-50
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A25L05PMF-50 Summary of contents
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Preliminary Document Title 8 Mbit, Low Voltage, Serial Flash Memory With 50MHz SPI Bus Interface Revision History Rev. No. History 0.0 Initial issue PRELIMINARY (May, 2005, Version 0.0) 8 Mbit, Low Voltage, Serial Flash Memory With 50 MHz SPI Bus ...
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Preliminary FEATURES 8 Mbit of Flash Memory Flexible Sector Architecture (4/4/8/16/32)KB/64x15 KB Bulk Erase (8 Mbit) in 10s (typical) Sector Erase (512 Kbit (typical) Page Program (up to 256 Bytes) in 3ms (typical) 2.7 to 3.6V Single Supply ...
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Block Diagram HOLD W Control Logic Address register and Counter Pin Descriptions Pin No. Description C Serial Clock D Serial Data Input Q Serial Data Output Chip Select S Write Protect W Hold HOLD Vcc Supply ...
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SIGNAL DESCRIPTION Serial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D). This input signal is used ...
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Figure 1. Bus Master and Memory Devices on the SPI Bus SDO SPI Interface with SDI (CPOL, CPHA (1, 1) Bus Master (ST6, ST7, ST9, ST10, Other) CS3 CS2 CS1 Note: The Write Protect ( W ...
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OPERATING FEATURES Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program ...
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Table 1. Protected Area Sizes Status Register Content BP2 Bit BP1 Bit BP0 Bit Note: 1. ...
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MEMORY ORGANIZATION The memory is organized as: 1,048,576 bytes (8 bits each) 16 sectors (one (4/4/8/16/32) Kbytes & 64x15 Kbytes each) 4096 pages (256 bytes each). Table 2. Memory Organization Sector ...
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INSTRUCTIONS All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of S Serial Clock (C) after Chip Select ( one-byte instruction ...
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Write Enable (WREN) The Write Enable (WREN) instruction (Figure 4.) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write ...
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Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When ...
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Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) ...
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Table 5. Protection Modes SRWD W Mode Bit Signal 1 0 Status Register is Writable (if the WREN instruction has set the Software Protected WEL bit) The values in the 0 0 (SPM) SRWD, BP2, BP1 and BP0 bits can ...
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Read Data Bytes (READ) The device is first selected by driving Chip Select ( instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial ...
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Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select ( instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a dummy byte, ...
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Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write ...
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Sector Erase (SE) The Sector Erase (SE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device ...
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Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device ...
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Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device ...
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Read Device Identification (RDID) The Read Identification (RDID) instruction allows the 8-bit manufacturer identification code to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 37h, plus the continuation ...
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Release from Deep Power-down and Read Electronic Signature (RES) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down and Read Electronic Signature (RES) instruction. Executing this instruction takes the device ...
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Figure 16. Release from Deep Power-down (RES) Instruction Sequence High Impedance Q S Driving Chip Select ( ) High after the 8-bit instruction byte has been received by the device, but before the whole of ...
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POWER-UP AND POWER-DOWN At Power-up and Power-down, the device must not be selected S (that is Chip Select ( ) must follow the voltage applied on V until V reaches the correct value (min) at Power-up, and then ...
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Figure 17-2. Power-Down and Voltage Drop V V (max (min (low) CC Table 6. Power-Up Timing and V Symbol (min) to low VSL Time delay to Write instruction PUW ...
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Absolute Maximum Ratings* Storage Temperature (TSTG -65° 150°C Lead Temperature during Soldering (Note 1) Input and Output Voltage (with respect to Ground) (VID ...
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Table 10. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Standby Current CC1 I Deep Power-down Current CC2 I Operating Current (READ) CC3 I Operating Current (PP) CC4 I Operating Current (WRSR) CC5 ...
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Figure 18. AC Measurement I/O Waveform 0.8V 0.2V PRELIMINARY (May 2005, Version 0.0) Input Levels Timing Reference Levels A25L80P Input and Output 0.7V CC 0.5V CC 0.3V CC AMIC Technology Corp. ...
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Table 13. AC Characteristics Alt. Symbol f f Clock Frequency for the following instructions: FAST_READ, PP SE, BE, DP, RES, RDID, WREN, WRDI, RDSR, WRSR f Clock Frequency for READ instructions Clock High Time ...
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Figure 19. Serial Input Timing S tCHSL C tDVCH D Q Figure 20. Write Protect Setup and Hold Timing during WRSR when SRWD=1 W tSHSL PRELIMINARY (May 2005, Version 0.0) tSLCH tCHDX MSB IN High Impedance ...
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Hold Timing Figure 21 HOLD Figure 22. Output Timing S C tCLQV tCLQX tCLQX D Q ADDR.LSB IN PRELIMINARY (May 2005, Version 0.0) tHLCH tCHHL tCHHH tHLQZ tCH tCLQV 29 A25L80P tHHCH tHHQX tCL LSB OUT ...
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Part Numbering Scheme A25 Optional PRELIMINARY (May 2005, Version 0. Package Material Blank: normal F: PB free Temperature* Speed - MHz Operating Frequency Package MW = SOP8 MF = SOP16 ...
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Ordering Information Part No. Speed (MHz) A25L80PMW-50 A25L80PMW-50F 50 A25L80PMW-50U A25L80PMW-50UF A25L80PMF-50 A25L80PMF-50F 50 A25L80PMF-50U A25L80PMF-50UF -U is for industrial operating temperature range: -40 PRELIMINARY (May 2005, Version 0.0) Active Read Program/Erase Current Current Typ. (mA) Typ. (mA ...
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Package Information SOP 8L (209mil) Outline Dimensions PRELIMINARY (May 2005, Version 0. GAGE PLANE SEATING PLANE b Dimensions in mm Symbol Min Nom A 1.75 1.95 A 0.05 0. 1.70 1.80 2 ...
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Package Information SOP 16L (300mil) Outline Dimensions 16 1 0.016 typ. PRELIMINARY (May 2005, Version 0. 0.050 typ. SEATING PLANE 0.004max. Dimensions in inch Symbol Min A 0.093 A 0.004 1 D 0.398 E 0.291 H 0.394 ...