UPD784036GCA NEC [NEC], UPD784036GCA Datasheet
UPD784036GCA
Related parts for UPD784036GCA
UPD784036GCA Summary of contents
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SINGLE-CHIP MICROCONTROLLER The PD784036( product of the PD784038 sub-series in the 78K/IV series. A stricter quality assurance program applies to the PD784036(A) than the PD784036 (standard product). In terms of the NEC quality, the PD784036(A) is classified ...
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ORDERING INFORMATION Part number PD784035GC(A)- -3B9 80-pin plastic QFP (14 PD784036GC(A)- -3B9 80-pin plastic QFP (14 Remark is a ROM code suffix. QUALITY GRADE Part number PD784035GC(A)- -3B9 80-pin plastic QFP (14 PD784036GC(A)- -3B9 80-pin plastic QFP (14 Remark is ...
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SERIES PRODUCT DEVELOPMENT DIAGRAM : Under mass production : Under development Standard models Enhanced internal memory capacity, PD784026 pin compatible with the PD784026 Enhanced A/D, Multimaster I 16-bit timer, and power management 100 pins, enhanced I/O and internal memory ...
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FUNCTIONS Product Item Number of basic instructions 113 (mnemonics) General-purpose register 8 bits 16 registers Minimum instruction execution 125 ns/250 ns/500 ns/1 000 ns (at 32 MHz) time Internal 48K bytes ROM memory 2 048 bytes RAM Memory space Program ...
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DIFFERENCES BETWEEN PD784038 SUB-SERIES SPECIAL PRODUCTS .................... 2. DIFFERENCES BETWEEN STANDARD AND SPECIAL PRODUCTS .................................. 3. PIN CONFIGURATION (TOP VIEW) ......................................................................................... 4. BLOCK DIAGRAM ..................................................................................................................... 5. LIST OF PIN FUNCTIONS ......................................................................................................... 5.1 Port Pins ............................................................................................................................................ 5.2 Non-Port Pins ................................................................................................................................... ...
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LOCAL BUS INTERFACE ......................................................................................................... 9.1 Memory Expansion .......................................................................................................................... 9.2 Memory Space .................................................................................................................................. 9.3 Programmable Wait ......................................................................................................................... 9.4 Pseudo-Static RAM Refresh Function .......................................................................................... 9.5 Bus Hold Function ........................................................................................................................... 10. STANDBY FUNCTION ............................................................................................................... 11. RESET FUNCTION ..................................................................................................................... 12. INSTRUCTION SET .................................................................................................................... ...
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DIFFERENCES BETWEEN PD784038 SUB-SERIES SPECIAL PRODUCTS The only difference between the PD784031(A), PD784035(A), and PD784036(A) is their capacity of internal memory. The PD78P4038(A) is produced by replacing the masked ROM in the PD784036(A) with 128K-byte one-time PROM or EPROM. ...
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PIN CONFIGURATION (TOP VIEW) • 80-pin plastic QFP (14 14 mm) PD784031GC(A)- -3B9, PD784036GC(A P32/SCK0/SCL 1 P33/SO0/SDA 2 P34/ ...
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A8-A19 : Address bus AD0-AD7 : Address/data bus ANI0-ANI7 : Analog input ANO0, ANO1 : Analog output ASCK, ASCK2 : Asynchronous serial clock ASTB : Address strobe AV : Analog power supply DD AV -AV : Reference voltage REF1 REF3 ...
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BLOCK DIAGRAM NMI Programmable interrupt controller INTP0-INTP5 INTP3 Timer/counter 0 TO0 (16 bits) TO1 Timer/counter 1 INTP0 (16 bits) INTP1 INTP2/CI Timer/counter 2 TO2 (16 bits) TO3 Timer 3 (16 bits) P00-P03 Real-time output port P04-P07 PWM0 PWM PWM1 ...
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LIST OF PIN FUNCTIONS 5.1 Port Pins (1/2) Pin I/O Dual-function P00-P07 I/O - P10 PWM0 I/O P11 PWM1 P12 ASCK2/SCK2 P13 RxD2/SI2 P14 TxD2/SO2 P15-P17 - P20 NMI Input P21 INTP0 P22 INTP1 P23 INTP2/CI P24 INTP3 P25 ...
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Port Pins (2/2) Pin Dual-function I/O P60-P63 A16-A19 I/O P64 RD P65 WR P66 WAIT/HLDRQ P67 REFRQ/HLDAK P70-P77 ANI0-ANI7 I/O 12 PD784035(A), 784036(A) Function Port 6 (P6): 8-bit I/O port. Inputs and outputs can be specified bit by bit. ...
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Non-Port Pins (1/2) Pin I/O Dual-function TO0-TO3 Output P34-P37 CI Input P23/INTP2 R D Input P30/SI1 P13/SI2 Output P31/SO1 P14/SO2 X ASCK Input P25/INTP4/SCK1 ASCK2 P12/SCK2 SDA I/O P33/SO0 SI0 ...
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Non-Port Pins (2/2) Pin I/O Dual-function RESET Input - X1 Input - X2 - ANI0-ANI7 Input P70-P77 ANO0, ANO1 Output - REF1 REF2 REF3 Note 1 V DD0 V ...
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I/O Circuits for Pins and Handling of Unused Pins Table 5-1 describes the types of I/O circuits for pins and the handling of unused pins. See Figure 5-1 for the configuration of these various types of I/O circuits. Table ...
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Table 5-1. Types of I/O Circuits for Pins and Handling of Unused Pins (2/2) Pin I/O circuit type RESET 2 TEST 1-A AV -AV - REF1 REF3 Caution When I/O mode of an I/O dual-function pin ...
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Figure 5-1. I/O Circuits for Pins Type 1-A V DD0 SS0 Type 2 IN Schmitt trigger input with hysteresis characteristics V Type 4-B DD0 Data P Output N disable V Push-pull output which can output high ...
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CPU ARCHITECTURE 6.1 Memory Space A 1M-byte memory space can be accessed. By using a LOCATION instruction, mode for mapping internal data areas (special function registers and internal RAM) can be selected. A LOCATION instruction must always be executed ...
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When the LOCATION 0 instruction is executed External memory Note 1 (960K bytes Special function registers (SFRs Note 1 0 ...
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When the LOCATION 0 instruction is executed F FFF FH External memory Note 1 (960K bytes FFF FH Special function registers (SFRs) 0 FFDFH Note 1 0 FFD0 H (256 bytes ...
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CPU Registers 6.2.1 General-purpose registers A set of general-purpose registers consists of sixteen general-purpose 8-bit registers. Two 8-bit general-purpose registers can be combined to form a 16-bit general-purpose register. Moreover, four 16-bit general-purpose registers, when combined with an 8-bit ...
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Control registers (1) Program counter (PC) This register is a 20-bit program counter. The program counter is automatically updated by program execution. Figure 6-4. Format of Program Counter (PC (2) Program status word (PSW) This register holds ...
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Special function registers (SFRs) The special function registers are registers with special functions such as mode registers and control registers for built-in peripheral hardware. The special function registers are mapped onto the 256-byte space between 0FF00H Note and 0FFFFH ...
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Table 6-1. Special Function Registers (SFRs) (1/4) Address Note Special function register (SFR) name 0FF00H Port 0 0FF01H Port 1 0FF02H Port 2 0FF03H Port 3 0FF04H Port 4 0FF05H Port 5 0FF06H Port 6 0FF07H Port 7 0FF0EH Port ...
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Table 6-1. Special Function Registers (SFRs) (2/4) Address Note 1 Special function register (SFR) name 0FF36H Capture register (timer/counter 0) 0FF38H Capture register L (timer/counter 1) 0FF39H Capture register H (timer/counter 1) 0FF3AH Capture register L (timer/counter 2) 0FF3BH Capture ...
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Table 6-1. Special Function Registers (SFRs) (3/4) Address Note 1 Special function register (SFR) name 0FF84H Synchronous serial interface mode register 1 0FF85H Synchronous serial interface mode register 2 0FF86H Serial shift register 0FF88H Asynchronous serial interface mode register 0FF89H ...
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Table 6-1. Special Function Registers (SFRs) (4/4) Address Note Special function register (SFR) name 0FFCCH Refresh mode register 0FFCDH Refresh area specification register 0FFCFH Oscillation settling time specification register 0FFD0H- External SFR area 0FFDFH 0FFE0H Interrupt control register (INTP0) 0FFE1H ...
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PERIPHERAL HARDWARE FUNCTIONS 7.1 Ports The ports shown in Figure 7-1 are provided to enable the application of wide-ranging control. Table 7-1 lists the functions of the ports. For the inputs to port 0 to port 6, a built-in ...
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Port name Pin Port 0 P00-P07 • Bit-by-bit input/output setting supported • Operable as 4-bit real-time outputs (P00-P03, P04-P07) • Capable of driving transistors Port 1 P10-P17 • Bit-by-bit input/output setting supported • Capable of driving LEDs Port 2 P20-P27 ...
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Figure 7-3. Examples of Using Oscillator • When EXTC bit of OSTS = 1 PD784036( PD74HC04, etc. Caution When using the clock generator, to avoid problems caused by influences such as stray capacitance, run all wiring within the ...
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Real-Time Output Port The real-time output port outputs data stored in the buffer, synchronized with a timer/counter 1 match interrupt or external interrupt. Thus, pulse output that is free of jitter can be obtained. Therefore, the real-time output port ...
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Timers/Counters Three timer/counter units and one timer unit are incorporated. Moreover, seven interrupt requests are supported, allowing these units to function as seven timer/counter units. Table 7-2. Timer/Counter Operation Item Count pulse width 8 bits 16 bits Operating mode ...
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Figure 7-5. Timer/Counter Block Diagram Timer/counter Prescaler xx Edge INTP3 detection Timer/counter Prescaler xx Event input Edge INTP0 detection Timer/counter Prescaler xx INTP2/CI Edge detection INTP2 Edge INTP1 detection Timer 3 ...
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PWM Output (PWM0, PWM1) Two channels of PWM (pulse width modulation) output circuitry with a resolution of 12 bits and a repetition frequency of 62.5 kHz ( MHz) are incorporated. Low or high active level can be ...
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A/D Converter An analog/digital (A/D) converter having 8 multiplexed analog inputs (ANI0-ANI7) is incorporated. The successive approximation system is used for conversion. The result of conversion is held in the 8-bit A/D conversion result register (ADCR). Thus, speedy high-precision ...
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D/A Converter Two digital/analog (D/A) converter channels of voltage output type, having a resolution of 8 bits, are incorporated. An R-2R resistor ladder system is used for conversion. By writing the value to be subject to D/A conversion in ...
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Serial Interface Three independent serial interface channels are incorporated. • Asynchronous serial interface (UART)/three-wire serial I/O (IOE) • Synchronous serial interface (CSI) • Three-wire serial I/O (IOE) • Two-wire serial I/O (IOE) So, communication with points external to the ...
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Asynchronous serial interface/three-wire serial I/O (UART/IOE) Two serial interface channels are available; for each channel, asynchronous serial interface mode or three-wire serial I/O mode can be selected. (1) Asynchronous serial interface mode In this mode, 1-byte data is transferred ...
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Three-wire serial I/O mode In this mode, the master device makes the serial clock active to start transmission, then transfers 1-byte data in phase with the clock. This mode is designed for communication with a device incorporating a conventional ...
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Synchronous serial interface (CSI) With this interface, the master device makes the serial clock active to start transmission, then transfers 1-byte data in phase with the clock. Figure 7-12. Block Diagram of Synchronous Serial Interface SI0 SO0/SDA N-ch open-drain ...
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Three-wire serial I/O mode This mode is designed for communication with a device incorporating a conventional synchronous serial interface. Basically, three lines are used for communication: the serial clock line (SCK0) and serial data lines (SI0 and SO0). In ...
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Edge Detection Function The interrupt input pins (NMI, INTP0-INTP5) are used to apply not only interrupt requests but also trigger signals for the built-in circuits. As these pins are triggered by an edge (rising or falling input ...
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INTERRUPT FUNCTION Table 8-1 lists the interrupt request handling modes. These modes are selected by software. Table 8-1. Interrupt Request Handling Modes Handling mode Handled by Vectored interrupt Software Branches to a handling routine for execution (arbitrary handling). Context ...
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Default Type priority Name Software - BRK instruction BRKCS instruction Operand error Nonmaskable - NMI WDT Maskable 0 (highest) INTP0 1 INTP1 2 INTP2 3 INTP3 4 INTC00 5 INTC01 6 INTC10 7 INTC11 8 INTC20 9 INTC21 10 INTC30 ...
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Vectored Interrupt When a branch to an interrupt handling routine occurs, the vector table address corresponding to the interrupt source is used as the branch address. Interrupt handling by the CPU consists of the following operations: • When a ...
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Context Switching When an interrupt request is generated, or when the BRKCS instruction is executed, an appropriate register bank is selected by the hardware. Then, a branch to a vector address stored in that register bank occurs. At the ...
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Examples of Macro Service Applications (1) Serial interface transmission TxD Each time a macro service request (INTST) is generated, the next transmission data is transferred from memory to TXS. When data n (last byte) has been transferred to TXS ...
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Real-time output port INTC10 and INTC11 function as the output triggers for the real-time output ports. For these triggers, the macro service can simultaneously set the next output pattern and interval. Therefore, INTC10 and INTC11 can be used to ...
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LOCAL BUS INTERFACE The local bus interface enables the connection of external memory and I/O devices (memory-mapped I/O). It supports a 1M-byte memory space. (See Figure 9-1.) Figure 9-1. Example of Local Bus Interface PD784036(A) A16-A19 RD WR REFRQ ...
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Memory Space The 1M-byte memory space is divided into eight spaces, each having a logical address. Each of these spaces can be controlled using the programmable wait and pseudo-static RAM refresh functions. FFFFFH 80000H 7FFFFH 40000H 3FFFFH 20000H 1FFFFH ...
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Programmable Wait When the memory space is divided into eight spaces, a wait state can be separately inserted for each memory space while the signal is active. This prevents the overall system efficiency from being degraded ...
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STANDBY FUNCTION The standby function allows the power consumption of the chip to be reduced. The following standby modes are supported: • HALT mode : The CPU operation clock is stopped. By occasionally inserting the HALT mode during normal ...
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RESET FUNCTION Applying a low-level signal to the RESET pin initializes the internal hardware (reset status). When the RESET input makes a low-to-high transition, the following data is loaded into the program counter (PC): • Eight low-order bits of ...
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INSTRUCTION SET (1) 8-bit instructions (The instructions enclosed in parentheses are implemented by a combination of operands, where A is described as r.) MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, ...
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AX is described as rp.) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, ...
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WHL is described as rg.) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP Table 12-3. Instructions Implemented by 24-Bit Addressing 2nd operand #imm24 WHL 1st ...
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Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET Table 12-4. Bit Manipulation Instructions Implemented by Addressing 2nd operand CY saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit 1st operand !addr16.bit !!addr24.bit CY MOV1 AND1 ...
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Call/return instructions and branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, ...
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ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (T Parameter Symbol Supply voltage Input voltage V I Output voltage V O Output low current I OL Output high current I OH A/D converter reference input AV ...
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OPERATING CONDITIONS • Operating ambient temperature (T • Rise time and fall time ( (at pins which are not specified 200 • Power supply voltage and clock cycle time Figure 13-1. ...
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OSCILLATOR CHARACTERISTICS (T Resonator Recommended circuit Ceramic resonator or crystal V X1 SS1 C1 External clock X1 HCMOS inverter Caution When using the system clock generator, run wires in the portion surrounded by broken lines according to the following rules ...
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OSCILLATOR CHARACTERISTICS (T Resonator Recommended circuit Ceramic resonator or crystal V X1 SS1 C1 External clock X1 HCMOS inverter Caution When using the system clock generator, run wires in the portion surrounded by broken lines according to the following rules ...
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DC CHARACTERISTICS (T = - Parameter Symbol Input low voltage V For pins other than those described in IL1 Notes and 4 V For pins described in Notes and ...
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DC CHARACTERISTICS (T = - Parameter Symbol Input leakage current LI For pins other than X1 when EXTC = 0 Output leakage current Operation mode V supply ...
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AC CHARACTERISTICS (T = - (1) Read/write operation (1/2) Parameter Symbol Address setup time t V SAST ASTB high-level width t V WSTH Address hold time (to ASTB ) t V HSTLA Address hold time ...
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Read/write operation (2/2) Parameter Symbol Data setup time ( SODW Note Data hold time ( HWOD Delay from WR to ASTB t DWST WR low-level width t V WWL Note The ...
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External wait timing Symbol Parameter t Delay from address to WAIT input V DAWT Delay from ASTB to WAIT input t V DSTWT t Hold time from ASTB to WAIT V HSTWTH Delay from ASTB to WAIT t V ...
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SERIAL OPERATION (T = - (1) CSI Parameter Symbol Serial clock cycle time (SCK0) t Input CYSK0 Output Serial clock low-level width t Input WSKL0 (SCK0) Output Serial clock high-level width t Input WSKH0 (SCK0) ...
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IOE1, IOE2 Parameter Symbol Serial clock cycle time t Input CYSK1 (SCK1, SCK2) Output Serial clock low-level width t Input WSKL1 (SCK1, SCK2) Output Serial clock high-level width t Input WSKH1 (SCK1, SCK2) Output Setup time for SI1 and ...
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CLOCK OUTPUT OPERATION Parameter Symbol t CLKOUT cycle time CYCL CLKOUT low-level width t V CLL t CLKOUT high-level width V CLH t CLKOUT rise time V CLR CLKOUT fall time t V CLF Remarks n: Divided frequency ratio set ...
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A/D CONVERTER CHARACTERISTICS (T = - Parameter Symbol Resolution Total error Note Note Linearity calibration Quantization error Conversion time CONV Sampling time ...
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D/A CONVERTER CHARACTERISTICS (T Parameter Symbol Resolution Total error Load conditions Load conditions Settling time Load conditions Output resistance R DACS0 ...
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DATA RETENTION CHARACTERISTICS (T Parameter Symbol Data retention voltage V STOP mode DDDR Data retention current I V DDDR DDDR V DDDR V rise time t RVD DD V fall time t DD FVD V hold time t DD HVD ...
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TIMING WAVEFORM (1) Read operation t WSTH ASTB t SAST t HSTLA A8-A19 AD0-AD7 t DSTR t DAR RD (2) Write operation t WSTH ASTB t SAST t HSTLA A8-A19 AD0-AD7 t DSTW t DAW DSTID t ...
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HOLD TIMING ADTB, A8-A19, AD0-AD7, RD FHQC t DCFHA HLDRQ t DHQHHAH HLDAK EXTERNAL WAIT SIGNAL INPUT TIMING (1) Read operation ASTB t DSTWT A8-A19 AD0-AD7 t DAWT RD WAIT (2) Write operation ASTB t DSTWT A8-A19 AD0-AD7 ...
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REFRESH TIMING WAVEFORM (1) Random read/write cycle t RC ASTB (2) When refresh memory is accessed for a read and write at the same time ASTB RD DSTRFQ REFRQ t WRFQL (3) Refresh after ...
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SERIAL OPERATION (1) CSI t WSKL0 SCK t CYSK0 SI SO (2) IOE1, IOE2 t WSKL1 SCK t CYSK1 SI SO (3) UART, UART2 ASCK, ASCK2 PD784035(A), 784036(A) t WSKH0 t t DSBSK1 HSBSK1 Output data t WSKH1 t t ...
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CLOCK OUTPUT TIMING CLKOUT t CLR INTERRUPT REQUEST INPUT TIMING NMI INTP0 CI, INTP1-INTP3 INTP4, INTP5 RESET INPUT TIMING RESET CLH CLL t CLF t CYCL t t WNIH WNIL t t WIT0H WIT0L t t WIT1H ...
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EXTERNAL CLOCK TIMING DATA RETENTION CHARACTERISTICS STOP mode setting HVD FVD RESET NMI (Clearing by falling edge) NMI (Clearing by rising edge) PD784035(A), 784036( WXH WXL CYX V ...
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PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14x14 NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. Remark The shape and material ...
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RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the PD784035(A) and PD784036(A). For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices ...
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APPENDIX A DEVELOPMENT TOOLS The following development tools are available for system development using the PD784036(A). See also (5). (1) Language processing software RA78K4 CC78K4 DF784038 CC78K4-L (2) PROM write tools PG-1500 PA-78P4026GC PG-1500 controller (3) Debugging tools • When ...
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When using the in-circuit emulator IE-784000-R IE-784000-R IE-70000-98-IF-B IE-70000-98-IF-C Note IE-70000-98N-IF-B IE-70000-PC-IF-B IE-70000-PC-IF-C Note IE-78000-R-SV3 Note IE-784038-NS-EM1 Note IE-784038-R-EM1 IE-78400-R-EM IE-78K4-R-EX2 Note EP-78230GC-R EV-9200GC-80 ID78K4 SM78K4 DF784038 Note Under development (4) Real-time OS RX78K/IV MX78K4 PD784035(A), 784036(A) In-circuit emulator ...
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Notes when using development tools • The ID78K-NS, ID78K4, and SM78K4 can be used in combination with the DF784038. • The CC78K and RX78K/IV can be used in combination with the RA78K4 and DF784038. • The NP-80GC is a ...
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APPENDIX B RELATED DOCUMENTS Documents Related to Devices Document name PD784035(A), 784036(A) Data Sheet PD784031(A) Data Sheet PD78P4038(A) Data Sheet PD784038, 784038Y Sub-Series User's Manual, Hardware PD784038 Sub-Series Special Function Registers 78K/IV Series User's Manual, Instruction 78K/IV Series Instruction Summary ...
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Documents Related to Software to Be Incorporated into the Product (User’s Manual) Document name 78K/IV Series Real-Time OS OS for 78K/IV Series MX78K4 Other Documents Document name IC PACKAGE MANUAL Semiconductor Mount Technology Manual Quality Grades on NEC Semiconductor Device ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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IEBus is a trademark of NEC Corporation. MS-DOS and Windows are registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT, and PC DOS are trademarks of IBM Corporation. HP9000 series 700 and HP-UX are ...
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They ...
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Some related documents may be preliminary versions. Note that, however, what documents are preliminary is not indicated in this document. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited ...