cx74063-26 Skyworks Solutions, Inc., cx74063-26 Datasheet - Page 11

• Manufacturer Part Number: cx74063-26
• Description: Transceiver Multi-band Gprs, Edge Applications With Power Ramping Controller Integrated Crystal Oscillator With Output
• Manufacturer: Skyworks Solutions, Inc.

A commonly used measure for receiver second-order distortion
is the second-order intercept point, IP2. For example, to ensure
that the unwanted baseband signals are 9 dB below the
wanted signal required under the AM suppression test for type
approval (see 3GPP TS 51.010-1), an input IP2 of 43 dBm is
required:
The CX74063-26 receiver includes a circuit that minimizes
second-order distortion. This IP2 calibration circuit effectively
compensates any second-order distortion in the receive chain
that would otherwise generate unwanted baseband signals in
the presence of strong interfering signals. When calibrated
correctly, the CX74063-26 IP2 meets the GSM AM suppression
test requirements in all bands with good margin.
To calibrate IP2, apply a strong RF signal at the receiver input
and observe the resulting DC voltage level change at the
receiver I/Q outputs. The exact frequency and level of the
signal applied for the purpose of the calibration are not critical.
The signal should, however, be within the receive band, but at
least 6 MHz offset from the frequency to which the receiver is
tuned. The level should be high enough tocause a notable DC
shift at the I/Q outputs. A recommended value is –30 dBm at
the LNA input, which applies to all three LNAs.
A set of I/Q compensation coefficients can then be
programmed to the device to minimize the DC voltage shift
resulting from the second-order distortion. When the DC due to
the interfering signal is minimized, the IP2 performance is
optimized.
Note:
103052A
SXENA, pin 38, must be held high, and a clock signal
must be present on XTAL, pin 34, during the
programming of the IP2 calibration coefficients in
register 3, see Table 18.
Figure 5. DC Offset Correction Timing (LNA On During Part of the DC Offset Correction Sequence)
RXENA
DC Offset Correction Loop 1
DC Offset Correction Loop 2
DC Offset Correction Loop 3
Front End
Enable
Note 1. t
T_H1
[781] 376-3000 I FAX [781] 376-3100 I [e-mail] I WWW.SKYWORKSINC.COM
, t
T_H2
, t
T_H3
Skyworks Solutions, Inc., Proprietary and Confidential
, and t
FEENA
Track mode
Track mode
Track mode
(Note 1)
t
T_H1
are programmed in Register 2.
(LNA off)
(Note 1)
t
FEENA
Hold mode (Loop
1)
(Note 1)
(Note 1)
t
t
T_H2
T_H3
(LNA on)
The IP2 calibration is a one-time factory calibration that should
be done for each band and each individual device for optimum
performance. The determined coefficients must be stored in
nonvolatile memory and programmed to the CX74063-26 upon
each power-up as part of device initialization. There are on-
chip registers that must be programmed through register 3
with the appropriate IP2 coefficients for the band in use.
As long as a supply voltage is maintained on pin 43, VDDBB,
the IP2 coefficients for I
programmed to the device remain in the registers. After the
supply voltage has been removed from VDDBB, the coefficients
must be re-programmed to the device again.
Synthesizer Section
The CX74063-26 includes a fully integrated UHF VCO with an
on-chip LC tank.
A single sigma-delta fractional-N synthesizer can phase-lock
the local oscillator used in both transmit and receive paths to a
precision frequency reference input. Fractional-N operation
offers low phase noise and fast settling times, allowing for
multiple slot applications such as GPRS. The CX74063-26
frequency stepping function with a 3 Hz resolution allows triple
band operation in both transmit and receive bands using a fully
integrated single integrated on-chip UHF VCO. The fine
synthesizer resolution allows direct compensation or
adjustment for reference frequency errors.
The fractional-N synthesizer consists of the following:
• VCO
• High frequency prescaler
• N-divider with a sigma-delta modulator
• Reference buffer and divider
• Fast phase frequency detector and charge pump
Hold mode (Loop
2)
Hold mode (Loop
3)
Start of RX slot
Lowband
101953A 4_012902
, I
Highband
Data Sheet I CX74063-26
, Q
Lowband
, Q
Highband
MAY 16, 2003
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