CY2SSTV16859LFC CYPRESS [Cypress Semiconductor], CY2SSTV16859LFC Datasheet

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CY2SSTV16859LFC

Manufacturer Part Number
CY2SSTV16859LFC
Description
13-Bit to 26-Bit Registered Buffer PC2700-/PC3200-Compliant
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Cypress Semiconductor Corporation
Document #: 38-07463 Rev. *B
Features
Description
This 13-bit to 26-bit registered buffer is designed for 2.3V to
2.7 VDD operations.
All inputs are compatible with the JEDEC Standard for SSTL-2,
except the LVCMOS reset (RESET#) input. All outputs are
SSTL_2, Class II compatible.
Block Diagram
• Differential clock inputs up to 280 MHz
• Supports LVTTL switching levels on the RESET# pin
• Output drivers have controlled edge rates, so no
• Two KV ESD protection
• Latch-up performance exceeds 100 mA per JESD78,
• 64-pin TSSOP/JEDEC and 56-pin QFN package avail-
• JEDEC specification supported
external resistors are required.
Class II
ability
RESET #
CLK #
CLK
D1
VREF
To 12 Other Channels
D
C
R
Q1A
Q1B
3901 North First Street
13-Bit to 26-Bit Registered Buffer
The CY2SSTV16859 operates from a differential clock (CLK
and CLK#) of frequency up to 280 MHz. Data are registered at
crossing of CLK going high and CLK# going low.
When RESET# is low, the differential input receivers are
disabled, and undriven (floating) data and clock inputs are
allowed. The LVCMOS RESET# input must always be held at
a valid logic high or low level.
To ensure defined outputs from the register before a stable
clock has been supplied, RESET# must be held in the low
state during power up.
In the DDR DIMM application, RESET# is completely
asynchronous with respect to CLK# and CLK. Therefore, no
timing relationship can be guaranteed between the two. When
entering reset, the register is cleared and the outputs are
driven low quickly, relative to the time to disable the differential
input receivers, thus ensuring no glitches on the output.
However, when coming out of reset, the register becomes
active quickly, relative to the time to enable the differential
input receivers.
PC2700-/PC3200-Compliant
Pin Configuration
VDDQ
VDDQ
VDDQ
Q13A
Q12A
Q11A
Q10A
Q13B
Q12B
Q11B
Q10B
GND
GND
GND
San Jose
Q9A
Q8A
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
Q1A
Q9B
Q8B
Q7B
Q6B
Q5B
Q4B
Q3B
Q2B
Q1B
64 TSSOP Package
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
,
CA 95134
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CY2SSTV16859
VDDQ
GND
D13
D12
VDD
VDDQ
GND
D11
D10
D9
GND
D8
D7
RESET #
GND
CLK #
CLK
VDDQ
VDD
VREF
D6
GND
D5
D4
D3
GND
VDDQ
VDD
D2
D1
GND
VDDQ
Revised July 29, 2003
408-943-2600

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CY2SSTV16859LFC Summary of contents

Page 1

Features • Differential clock inputs up to 280 MHz • Supports LVTTL switching levels on the RESET# pin • Output drivers have controlled edge rates external resistors are required. • Two KV ESD protection • Latch-up performance exceeds ...

Page 2

Pin Configuration (continued) Q7A Q6A Q5A Q4A Q3A Q2A Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B Pin Description Pin TSSOP 51 7,15,34,39,43,50,54,58,63 37,46,60 6,18,27,33,38,47,59,64 45 16,14,13,12,11,10,9,8,5,4,3,2,1 32,31,30,29,28,25,24,23,22,21,20, 19,17 35,36,40,41,42,44,52,53,55,56,57, 61,62 48,49 [1,2,3] Table 1. Function Table RESET# CLK H ...

Page 3

Absolute Maximum Conditions Parameter Description [6] V Terminal Voltage with respect to V TERM [7] V Terminal Voltage with respect to V TERM T Storage Temperature STG I DC Output Current OUT I Continuous Clamp Current IK I Continuous Clamp ...

Page 4

DC Electrical Specifications Parameter Description I Dynamic RESET DDD operating – clock CLK and CLK# switching 50% duty only cycle Dynamic RESET operating – per CLK and CLK# switching 50% duty each data input cycle. One ...

Page 5

Output Buffer Characteristics Table 3. Output Buffer Voltage vs. Current (V/I) Characteristics Voltage (V) Min. I(mA 0.1 6 0.2 10 0.3 15 0.4 19 0.5 23 0.6 27 0.7 30 0.8 34 0.9 36 1.0 38 1.1 40 ...

Page 6

... TSSOP– Tape and Reel CY2SSTV16859ZI 64-pin TSSOP CY2SSTV16859ZIT 64-pin TSSOP – Tape and Reel CY2SSTV16859LFC 56-pin QFN CY2SSTV16859LFCT 56-pin QFN – Tape and Reel CY2SSTV16859LFI 56-pin QFN CY2SSTV16859LFIT 56-pin QFN– Tape and Reel Notes: 14. All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz 50-ohm output slew rate = 1 V/ns ±20% (unless otherwise specified) ...

Page 7

Package Drawing and Dimension 64-lead Thin Shrunk Small Outline Package ( mm) Z64 All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07463 Rev. *B © Cypress Semiconductor ...

Page 8

Document History Page Document Title:CY2SSTV16859 13-Bit to 26-Bit Registered Buffer PC2700-/PC3200-Compliant Document Number: 38-07463 Issue REV. ECN No. Date ** 123052 04/14/03 *A 126277 04/21/02 *B 128326 07/30/03 Document #: 38-07463 Rev. *B Orig. of Change RGL New Data Sheet ...

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