88e3015 Marvell Semiconductor, Inc., 88e3015 Datasheet
88e3015
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88e3015 Summary of contents
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... Datasheet Integrated 10/100 Fast Ethernet Transceiver Doc. No. MV-S103657-00, Rev. C October 26, 2006 ...
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Document Status Advance This document contains design specifications for initial product development. Specifications may Information change without notice. Contact Marvell Field Application Engineers for more information. Preliminary This document contains preliminary data, and a revision of this document will be ...
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... IEEE 1149.1 JTAG Standard Test Access Port and Boundary Scan. The 88E3108 device is avail- able in Industrial grade (RoHS 6/6 compliant package only) The 88E3015 device, housed in a 56-pin QFN package, provides a cost-efficient, increased board savings option to the 88E3018. Copyright © 2006 Marvell ...
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... Crossover MDIP/N[1] FX Link SIGDET & Auto Negotiation XTAL_IN XTAL_OUT Clock/ RESETn Reset COMAn 2.5V CTRL25 Regulator 1.2V DIS_REG12 Regulator 88E3015 Device Functional Block Diagram Boundary JTAG Scan MDIP/N[0] Auto MDIX Crossover MDIP/N[1] FX Link SIGDET & Auto Negotiation XTAL_IN XTAL_OUT Clock/ RESETn Reset COMAn 2 ...
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... IGNAL ESCRIPTION 1.1 88E3015 Device 56-Pin QFN Pinout ............................................................................. 9 1.2 88E3018 Device 64-Pin QFN Pinout ........................................................................... 10 1.3 Pin Description ............................................................................................................ 11 1.3.1 Pin Type Definitions .......................................................................................................... 11 1.3.2 88E3015 56-Pin QFN Assignments - Alphabetical by Signal Name................................. 21 1.3.3 88E3018 64-Pin QFN Assignments - Alphabetical by Signal Name................................. ECTION UNCTIONAL 2.1 MAC Interface............................................................................................................... 24 2.1.1 Reduced Gigabit Media Independent Interface (RGMII)................................................... 24 2 ...
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... ECTION LECTRICAL PECIFICATIONS 4.1. Absolute Maximum Ratings ........................................................................................87 4.2. Recommended Operating Conditions ........................................................................88 4.3 Package Thermal Information .....................................................................................89 4.3.1 88E3015 Device 56-Pin QFN package ............................................................................ 89 4.3.2 88E3018 Device 64-Pin QFN package ............................................................................ 90 4.4 Current Consumption ..................................................................................................91 4.4.1 Current Consumption AVDD + Center Tap ...................................................................... 91 4.4.2 Current Consumption AVDDC.......................................................................................... 91 4.4.3 Current Consumption DVDD ............................................................................................ 92 4.4.4 Current Consumption VDDO + VDDOR........................................................................... 92 4 ...
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... Circuit Application ............................................................117 6.2 FX Interface to 3.3V Fiber Transceiver .....................................................................118 6.3 Transmitter - Receiver Diagram ................................................................................119 6.4 88E3018 to 88E3015 Backplane Connection - 100BASE-FX Interface...................120 6.5 88E3018 to Another Vendor’s PHY - 100BASE-FX Interface through a Backplane121 6.6 Marvell® PHY to Marvell PHY Direct Connection ....................................................122 Copyright © 2006 Marvell ...
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... Integrated 10/100 Fast Ethernet Transceiver ECTION RDER NFORMATION 7.1 Ordering Part Numbers and Package Markings ......................................................123 Doc. No. MV-S103657-00, Rev. C Page 8 Document Classification: Proprietary Information ............................................................... 123 CONFIDENTIAL Copyright © 2006 Marvell October 26, 2006, Advance ...
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... Section 1. Signal Description 1.1 88E3015 Device 56-Pin QFN Pinout The 88E3015 is manufactured in a 56-pin QFN. Figure 1: 88E3015 Integrated 10BASE-T/100BASE-TX Fast Ethernet Transceiver 56-Pin QFN Package RXD[1] 43 VDDOR 44 RX_CLK 45 RXD[2] 46 RXD[3] 47 VDDOR 48 VREF 49 TXD[0] 50 TXD[1] 51 TX_CLK 52 TXD[2] 53 TXD[3] 54 TX_CTRL 55 CONFIG[0] 56 Copyright © 2006 Marvell ...
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... Integrated 10/100 Fast Ethernet Transceiver 1.2 88E3018 Device 64-Pin QFN Pinout The 88E3018 is manufactured in a 64-pin QFN. Figure 2: 88E3018 Integrated 10BASE-T/100BASE-TX Fast Ethernet Transceiver 64-Pin QFN Package RX_CTRL 49 50 RXD[0] EPAD - VSS RXD[1] 51 VDDOR 52 RX_CLK 53 RXD[2] 54 RXD[3] 55 VDDOR 56 VREF 57 TXD[0] ...
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Pin Description 1.3.1 Pin Type Definitions Pi n Type D efin Input with hysteresis I/O Input and output I Input only O Output only PU Internal pull up PD Internal pull down D Open ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 2: RGMII Interface 8 8E301 5 88E30 18 Pin Name 52 60 TX_CLK/TXC 55 63 TX_CTRL/TX_CTL 54 62 TXD[3]/TD[ TXD[2]/TD[ TXD[1]/TD[ TXD[0]/TD[ RX_CLK/RXC 41 49 RX_CTRL/ RX_CTL 47 55 RXD[3]/RD[ RXD[2]/RD[ RXD[1]/RD[ RXD[0]/RD[0] Doc. No. MV-S103657-00, Rev. C ...
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Table 3: MII Interface 88E30 15 88E3 018 Pin Name 52 60 TX_CLK 54 62 TXD[ TXD[ TXD[ TXD[ TX_CTRL/TX_EN 45 53 RX_CLK 47 55 RXD[ RXD[ RXD[1] ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 3: MII Interface (Continued) 8 8E301 5 88E30 18 Pin Name 18 20 CRS 19 23 COL Doc. No. MV-S103657-00, Rev. C Page 14 Document Classification: Proprietary Information Ty pe Des cription O, Z MII Carrier Sense. CRS asserts when the receive medium is non-idle. CRS is asynchronous to RX_CLK, and TX_CLK. ...
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Table 4: Network Interface 88E3 015 88 E3018 Pin Nam MDIP[ MDIN[ MDIP[ MDIN[ SIGDET Table 5: Serial Management Interface 88E30 15 88E3 018 Pin Name 38 48 MDC ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 6: LED 8 8E301 5 88E30 18 Pin Name 8 9 LED[2]/Interrupt 7 8 LED[ LED[0] Table 7: JTAG 88 E3015 88E30 18 Pin Nam TDI -- 41 TMS -- 42 TCK -- 11 TRSTn -- 44 TDO Doc. No. MV-S103657-00, Rev. C Page 16 Document Classification: Proprietary Information Ty pe Des cription O Parallel LED outputs ...
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Table 8: Clock/Configuration/Reset 88E30 15 88E3 018 Pin Name 32 38 XTAL_IN 33 39 XTAL_OUT 3 3 CONFIG[ CONFIG[ CONFIG[ CONFIG[ RESETn 49 57 VREF 39 4 COMAn Copyright © 2006 Marvell ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 9: Regulator & Reference 8 8E301 5 88E30 18 Pin Name 28 33 RSET 10 12 DIS_REG12 15 17 CTRL25 Table 10: Test 88 E3015 88E30 18 Pin Nam HSDACP 30 35 HSDACN 27 32 TSTPT Doc. No. MV-S103657-00, Rev. C Page 18 Document Classification: Proprietary Information Ty pe ...
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Table 11: Power & Ground 88E30 15 88E3 018 Pin Name 24 28 AVDD 29 34 AVDDC 12 14 AVDDR AVDDX 4 5 DVDD VDDO ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 12: I/O State at Various Test or Reset Modes Pi n(s) I sol ate MDIP/ Active Active N[1:0] TX_CLK Tri-state Active RXD[0] Tri-state Active RXD[2] RXD[3] RXD[1] RX_DV RX_ER CRS COL RX_CLK Tri-state Active MDIO Active Active LED Active ...
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... QFN Assignments - Alphabetical by Signal Name Pin # Pin Name 24 AVDD 29 AVDDC 12 AVDDR 13 AVDDR 14 AVDDX 19 COL 39 COMAn 56 CONFIG[0] 1 CONFIG[1] 2 CONFIG[2] 3 CONFIG[3] 18 CRS 15 CTRL25 10 DIS_REG12 4 DVDD 11 DVDD 34 DVDD 30 HSDACN 31 HSDACP 5 LED[0] 7 LED[1] 8 LED[2] 38 MDC 25 MDIN[0] 22 MDIN[1] 35 MDIO 26 MDIP[0] 23 MDIP[ Copyright © 2006 Marvell ...
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... Integrated 10/100 Fast Ethernet Transceiver 1.3.3 88E3018 64-Pin QFN Assignments - Alphabetical by Signal Name Pin # Pin N ame 28 AVDD 34 AVDDC 14 AVDDR 15 AVDDR 16 AVDDX 23 COL 4 COMAn 64 CONFIG[0] 1 CONFIG[1] 2 CONFIG[2] 3 CONFIG[3] 20 CRS 17 CTRL25 12 DIS_REG12 5 DVDD 13 DVDD 40 DVDD 35 HSDACN 36 HSDACP 6 LED[0] 8 LED[1] 9 LED[2] 48 MDC 30 MDIN[0] 25 MDIN[1] ...
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... Section 2. Functional Description Figure 3 shows the functional block for each of the 88E3015/88E3018 devices. The transmitter and transmit PCS block are fully described on page 29. The receiver and receive PCS block are fully described on Figure 3: 88E3015 Device Functional Block Diagram MDIP/N[0] Auto MDIX ...
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... Differences,” on page 4. All ports on the devices operate in the same interface mode that is selected. 2.1.1 Reduced Gigabit Media Independent Interface (RGMII) The 88E3015/88E3018 device supports the RGMII specification (Version 1.2a, 9/22/2000, version 2.0, 04/2002 - instead of HSTL, it supports 2.5V SSTL_2.). Figure 5: RGMII Signal Diagram MAC The interface runs at 2.5 MHz for 10 Mbps and 25 MHz for 100 Mbps. The TX_CLK signal is always generated by the MAC, and the RX_CLK signal is generated by the PHY ...
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... Media Independent Interface (MII) The 88E3015/88E3018 device supports the Media Independent Interface. Figure 6: MII Signal Diagram MAC When the MII mode is selected, both TX_CLK and RX_CLK source 2.5 MHz and 25 MHz for 10 Mbps and 100 Mbps respectively. Copyright © 2006 Marvell October 26, 2006, Advance ...
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... Integrated 10/100 Fast Ethernet Transceiver 2.1.3 Source Synchronous MII The 88E3015/88E3018 device supports Source Synchronous MII. Figure 7: Source Synchronous MII Signal Diagram MAC The Source Synchronous MII is identical to the MII, except the TX_CLK is an input. Refer to Section 4.7 for timing details. Doc. No. MV-S103657-00, Rev. C ...
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Serial Management Interface The serial management interface provides access to the internal registers via the MDC and MDIO pins and is compliant to IEEE 802.3u section 22. MDC is the management data clock input and can run from DC ...
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... Integrated 10/100 Fast Ethernet Transceiver 2.2.2 Preamble Suppression The 88E3015/88E3018 devices are permanently programmed for preamble suppression. A minimum of one idle bit is required between operations. 2.2.3 Programming Interrupts When Register 22:11:8 is set to 1110, the interrupt functionality is mapped to the LED[2] pin.The interrupt function drives the LED[2] pin active whenever an interrupt event is enabled by programming register 18. The polarity of the interrupt signal is determined by Register 25 ...
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... Transmit and Receive Functions The transmit and receive paths for the 88E3015/88E3018 device are described in the following sections. 2.3.1 Transmit Side Network Interface 2.3.1.1 Multi-mode TX Digital to Analog Converter The 88E3015/88E3018 device incorporates a multi-mode transmit DAC to generate filtered MLT-3, NRZI, or Manchester coded symbols. The transmit DAC performs signal wave shaping to reduce EMI. The transmit DAC is designed for very low parasitic loading capacitances to improve the return loss requirement, which allows the use of low cost transformers ...
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... Integrated 10/100 Fast Ethernet Transceiver 2.3.3.4 Link Monitor The link monitor is responsible for determining if link is established with a link partner. In 10BASE-T mode, link monitor function is performed by detecting the presence of valid link pulses (NLPs) on the MDI± pins. In 100BASE-TX mode, link is established by scrambled idles. ...
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... The 88E3015/88E3018 devices support the use of next page during Auto-Negotiation. By default, the received base page and next page are stored in the Link Partner Ability register - Base Page (Register 5). The 88E3015/ 88E3018 devices have an option to write the received next page into the Link Partner Next Page register - Regis- ter 8 - (similar to the description provided in the IEEE 802 ...
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... When Register 16.14 is enabled, the Energy Detect +™ mode is enabled. In this mode, the PHY sends out a sin- gle 10 Mbps NLP (Normal Link Pulse) every one second. If the 88E3015/88E3018 devices are in Energy Detect+ mode, it can wake a connected device. The 88E3015/88E3018 devices also respond to MDC/MDIO. ...
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COMA Mode COMA mode shuts down the PHY into a low power state when it is not being used. When the PHY is in the COMA mode, the PHY is completely non-functional including register access. COMA mode is entered ...
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... Integrated 10/100 Fast Ethernet Transceiver 2.5 Regulators and Power Supplies The 88E3015/88E3018 device can operate from a single 2.5V or 3.3V supply if the regulators are used. If regula- tors are not used then a 2.5V and 1.2V supply are needed. usage. The VDDO supply can run at 2.5V or 3.3V and that the VDDOR supply can run at 2.5V or 3.3V. The 2.5V gener- ated by the 2 ...
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... DVDD DVDD is used as the 1.2V digital supply. DVDD can be supplied externally with 1.2V, or via the 1.2V regulator. All DVDD pins should be shorted together. A decoupling capacitor should be attached to pin 11 of the 88E3015 device and pin 13 of the 88E3018 device. 2.5.6 VDDO VDDO supplies the non-MAC Interface digital I/O pins. The voltage range is 2.5V or 3.3V. ...
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... Integrated 10/100 Fast Ethernet Transceiver 2.6 Hardware Configuration The 88E3015/88E3018 devices are configured by tying LED[2:0], CRS, COL, VDDO, or VSS to CONFIG[3:0]. After the deassertion of RESET the 88E3015/88E3018 will be hardware configured. Note LED[2], CRS, and COL should not be tied to CONFIG[2:0]. Use VDDO to set bits [1:0] of CONFIG[2:0] to ’ ...
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The 3 bits for each CONFIG pin are mapped as shown in Table 18: Configuration Mapping P in CONFIG[0] CONFIG[1] CONFIG[2] CONFIG[3] Each bit in the configuration is defined as shown in Table 19: Configuration Definition B its D e ...
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... Register 16.8 enables and disables the FEFI function. This bit has no effect in 10BASE-T and 100BASE-TX modes. 2.8 802.3ah Unidirectional Enable The 88E3015/88E3018 devices support the 802.3ah Unidirectional Enable function. When this function is enabled the PHY transmit path is enabled even if there is no link established. To enable unidirectional transmitting, all the following conditions must be met: • ...
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... TDR test can be performed either when there is no link partner or when the link partner is Auto-Negotiating or sending 10 Mbit idle link pulses. If the 88E3015/88E3018 devices receive a continuous signal for 125 ms, it will declare test failure because it cannot start the TDR test. In the test fail case, the received data is not valid. The results of the test are also summarized in Register 26.14:13 and 27.14:13. • ...
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... The Auto MDI/MDIX crossover function can be disabled via Register 16.5:4. The 88E3015/88E3018 devices are set to MDI mode by default if auto MDI/MDIX crossover is disabled at hard- ware reset. Auto MDI/MDIX should be disabled for 100BASE-FX mode. MDI should be forced for 100BASE-FX. ...
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LED Interface The LEDs can either be controlled by the PHY or controlled externally, independent of the state of the PHY. 2.11.1 Manual Override External control is achieved by writing to the PHY Manual LED Override register 25.5:0. Any ...
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... Integrated 10/100 Fast Ethernet Transceiver 2.11.2 PHY Control Manual override is disabled (25.5:4, 25.3:2, 25.1:0 is set to 00) then the LED behavior is defined by register 22.11:8, 22.7:4, and 22.3:0 (Table 23). If SPEED is selected then the LED behavior is further qualified by register 24.8:6, 24.5:3, and 24.2:0 (Table 24). See Table 23: PHY LED Control ...
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Table 23: PHY LED Control (Continued 22.7:4 LED1 LED1 Control. This is a global setting. 0000 = COLX 0001 = ERROR 0010 ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 23: PHY LED Control (Continued 22.3:0 LED0 LED0 Control. This is a global setting. 0000 = COLX 0001 = ERROR 0010 = DUPLEX 0011 = DUPLEX/COLX 0100 = SPEED 0101 = LINK 0110 = TX 0111 = RX 1010 = LINK/ACT ...
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Table 24: Speed Dependent Behavior 24.8:6 LED2 Speed LED 2 Speed Select 000 = Active for 10BASE-T Link 001 = Reserved 010 ...
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... Integrated 10/100 Fast Ethernet Transceiver 2.11.3 LED Polarity The polarity of the LED in the active state can be set through register 25.14:12. Table 25: LED Active Polarity 25.14 InvLED2 Invert LED2. This bit controls the active level of the LED2 pin. ...
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Automatic and Manual Impedance Calibration 2.12.1 MAC Interface Calibration Circuit The auto calibration is available for the MAC interface I/Os. The PHY runs the automatic calibration circuit with a 49 ohm impedance target by default after hardware reset. Other ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 26: Register 30 Page 10 - MAC Interface Calibration Definitions (Continued PMOS/NMOS select 1 = PMOS value is written when LATCH NMOS value is written when LATCH is ...
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Write to register 30 = b'000P PPPP 010N NNNN -- adjusts NMOS strength Where PPPPP is the 5 bit value for the PMOS strength. Where NNNNN is the 5 bit value for the NMOS strength. The value of PPPPP or ...
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... Integrated 10/100 Fast Ethernet Transceiver Figure 13: NMOS Output Impedance (1.8V, 2.5V) Trend Lines (TBD Example: The automatic calibration has a 50 ohm target, but if the MII trace impedance on board was 60 ohms, you see reflections from a scope capture taken at the destination ...
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Figure 15: Clean signal after manual calibration for the 60 ohm Copyright © 2006 Marvell October 26, 2006, Advance Document Classification: Proprietary Information Automatic and Manual Impedance Calibration CONFIDENTIAL Doc. No. MV-S103657-00, Rev. C Page 51 ...
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... Integrated 10/100 Fast Ethernet Transceiver 2.13 CRC Error Counter The CRC counter, normally found in MACs, is available in the 88E3015/88E3018 device. The error counter fea- ture is enabled through register writes and the counter is stored in an eight bit register. 2.13.1 Enabling The CRC Error Counter 2 ...
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... IEEE 1149.1 Controller The 88E3018 supports the IEEE1149.1 Test Access port and Boundary Scan. The 88E3015 does not support this feature. The IEEE 1149.1 standard defines a test access port and boundary-scan architecture for digital integrated circuits and for the digital portions of mixed analog/digital integrated circuits. ...
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... Integrated 10/100 Fast Ethernet Transceiver Sample allows a snapshot to be taken of the data flowing from the system pins to the on-chip test logic or vice versa, without interfering with normal operation. The snapshot is taken on the rising edge of TCK in the Capture- DR controller state, and the data can be viewed by shifting through the component's TDO output. ...
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Table 28: 88E3018 Boundary Scan Chain Order (Continued (MII) Output Enable RX_ER Output CRS Output COL Output 2.14.3 Extest Instruction The extest instruction allows circuitry external to the PHY (typically the board interconnections tested. ...
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... Integrated 10/100 Fast Ethernet Transceiver Section 3. Register Description The IEEE defines only 32 registers address space for the PHY. In order to extend the number of registers address space available a paging mechanism is used. For register address 30, register 29 bits are used to specify the page. There is no paging for registers 1 and 28. ...
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Table 30 defines the register types used in the register map. Table 30: Register Types Typ e D escr ip tio n LH Register field with latching high function. If status is high, then the register is set to a ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 31: Register Map PHY Control Register PHY Status Register PHY Identifier PHY Identifier Auto-Negotiation Advertisement Register Link Partner Ability Register (Base Page) Link Partner Ability Register (Next Page) Auto-Negotiation Expansion Register ...
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Table 32: PHY Control Register Register SWReset R/ Loopback R/W 13 SpeedLSB R/W 12 AnegEn R/W Copyright © 2006 Marvell October 26, 2006, Advance ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 32: PHY Control Register (Continued) Register PwrDwn R/W 10 Isolate R/W 9 RestartAneg R/ Duplex R/W 7 ColTest R/W 6 SpeedMSB RO 5 Unidirectional R/W Enable 4:0 Reserved RO Doc. No. MV-S103657-00, Rev. C Page 60 Document Classification: Proprietary Information ...
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Table 33: PHY Status Register Register 100T4 RO 14 100FDX RO 13 100HDX RO 12 10FDX RO 11 10HPX RO 10 100T2FDX RO 9 100T2HDX RO ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 33: PHY Status Register (Continued) Register Link RO JabberDet RO ExtdReg RO Doc. No. MV-S103657-00, Rev. C Page 62 Document Classification: Proprietary Information 0x0 ...
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Table 34: PHY Identifier Register 15:0 Organization- RO ally Unique Identifier Bit 3:18 Table 35: PHY Identifier Register ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 36: Auto-Negotiation Advertisement Register Register AnegAd R/W NxtPage 14 Ack RO 13 AnegAd R/W ReFault 12 Reserved R/W 11 AnegAd Asym- R/W metric Pause 10 AnegAd Pause R/W 9 AnegAd 100T4 R/W 8 AnegAd R/W 100FDX Doc. No. MV-S103657-00, Rev. C Page 64 Document Classification: Proprietary Information ...
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Table 36: Auto-Negotiation Advertisement Register (Continued) Register AnegAd R/W 100HDX 6 AnegAd 10FDX R/W 5 AnegAd 10HDX R/W 4:0 AnegAd Selec- R/W tor Copyright © 2006 ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 37: Link Partner Ability Register (Base Page) Register LPNxt Page RO 14 LPAck RO 13 LPRemote RO Fault 12:5 LPTechAble RO 4:0 LPSelector RO Doc. No. MV-S103657-00, Rev. C Page 66 Document Classification: Proprietary Information ...
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Table 38: Link Partner Ability Register (Next Page) Register LPNxtPage RO 14 LPAck RO 13 LPMessage RO 12 LPack2 RO 11 LPToggle RO 10:0 LPData RO ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 39: Auto-Negotiation Expansion Register Register 15:5 Reserved RO 4 ParFaultDet RO/LH 3 LPNxtPg Able RO 2 LocalNxtPg RO Able 1 RxNewPage RO/LH 0 LPAnegAble RO Doc. No. MV-S103657-00, Rev. C Page 68 Document Classification: Proprietary Information ...
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Table 40: Next Page Transmit Register Register TxNxtPage R/W 14 Reserved RO 13 TxMessage R/W 12 TxAck2 R/W 11 TxToggle RO 10:0 TxData R/W Table 41: ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 42: PHY Specific Control Register Register Reserved R/W 14 EDet R/W 13 DisNLP Check R/W 12 Reg8NxtPg R/W 11 DisNLPGen R/W 10 Reserved R/W 9 DisScrambler R/W 8 DisFEFI R/W Doc. No. MV-S103657-00, Rev. C Page 70 Document Classification: Proprietary Information ...
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Table 42: PHY Specific Control Register (Continued) Register ExtdDistance R/W 6 SIGDET Polar- R/W ity 5:4 AutoMDI[X] R/W 3 Reserved R/W 2 SQE Test R/W 1 ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 43: PHY Specific Status Register Register Reserved RO 14 ResSpeed RO 13 ResDuplex RO 12 RcvPage RO Resolved RO 10 RTLink RO 9:7 Reserved RES 6 MDI/MDIX RO 5 Reserved RES 4 Sleep RO Doc. No. MV-S103657-00, Rev. C Page 72 Document Classification: Proprietary Information ...
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Table 43: PHY Specific Status Register (Continued) Register 3:2 Reserved RES 1 RTPolarity RO 0 RTJabber RO Table 44: PHY Interrupt Enable Register ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 44: PHY Interrupt Enable Register MDI[x]IntEn R/W 5 Reserved RES 4 EDetIntEn R/W 3:2 Reserved RES 1 PolarityIntEn R/W 0 JabberIntEn R/W Doc. No. MV-S103657-00, Rev. C Page 74 Document Classification: Proprietary Information ...
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Table 45: PHY Interrupt Status Register Reserved RO 14 SpeedInt RO DuplexInt RO RxPageInt RO AnegDoneInt RO LinkInt ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 45: PHY Interrupt Status (Continued) Register JabberInt RO, LH Table 46: PHY Interrupt Port Summary Register 15:0 Reserved RO Table 47: Receive Error Counter Register ...
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Table 48: LED Parallel Select Register Register 15:12 Reserved R/W 11:8 LED2 R/W 7:4 LED1 R/W Copyright © 2006 Marvell October 26, 2006, Advance Document Classification: Proprietary ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 48: LED Parallel Select Register (Continued) Register 3:0 LED0 R/W Doc. No. MV-S103657-00, Rev. C Page 78 Document Classification: Proprietary Information 0x4 Retain LED0 Control. This is a global setting. ...
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Table 49: PHY LED Control Register Register Reserved RO 14:12 PulseStretch R/W 11:9 BlinkRate R/W 8:6 LED2 Speed R/W 5:3 LED1 Speed R/W Copyright © 2006 ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 49: PHY LED Control Register (Continued) Register 2:0 LED0 Speed R/W Table 50: PHY Manual LED Override Register Reserved R/W 14 InvLED2 R/W 13 InvLED1 R/W 12 InvLED0 R/W 11:6 Reserved R/W 5:4 ForceLED2 R/W 3:2 ForceLED1 R/W 1:0 ForceLED0 R/W Doc ...
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Table 51: VCT™ Register for MDIP/N[0] Pins Register EnVCT R/W, SC 14:13 VCTTst RO 12:8 AmpRfln RO 7:0 DistRfln RO Copyright © 2006 Marvell October 26, ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 52: VCT™ Register for MDIP/N[1] Pins Register Reserved RO 14:13 VCTTst RO 12:8 AmpRfln RO 7:0 DistRfln RO Doc. No. MV-S103657-00, Rev. C Page 82 Document Classification: Proprietary Information ...
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Table 53: PHY Specific Control Register II Register 15:12 Reserved R/W 11:10 MAC Interface R/W Mode 9:5 Reserved R/W 4 EnLineLpbk R/W 3 SoftwareMedia R/W Select 2 ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 54: Test Mode Select Register 15:5 Reserved R/W 4:0 Page R/W Table 55: CRC Status Register Register 30_9 15:8 CRC Error RO Count 7:1 Reserved R/W 0 CRC Enable R/W Doc. No. MV-S103657-00, Rev. C Page 84 Document Classification: Proprietary Information ...
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Table 56: MAC Interface Output Impedance Calibration Override Register 30_10 Restart Calibra- R/W, tion SC 14 Calibration RO Complete 13 Reserved R/W 12:8 PMOS Value R/W 7 ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 57: MAC Interface Output Impedance Target Register 30_11 15:7 Reserved RO 6:4 Calibration RW PMOS Target Impedance 3 Reserved RO 2:0 Calibration RW NMOS Target Impedance Doc. No. MV-S103657-00, Rev. C Page 86 Document Classification: Proprietary Information ...
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Section 4. Electrical Specifications 4.1. Absolute Maximum Ratings Stresses above those listed in Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect ...
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... Integrated 10/100 Fast Ethernet Transceiver 4.2. Recommended Operating Conditions Symbol Para meter 1 V AVDD supply DDA 1 V AVDDC supply DDAC 1 V AVDDR supply DDAR 1 V AVDDX supply DDAX 1 V DVDD supply VDDO supply DDO 1 V VDDOR supply DDOR RSET Internal bias reference ...
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... Package Thermal Information 4.3.1 88E3015 Device 56-Pin QFN package Symbol Parameter θ Thermal resistance - JA junction to ambient of the 56-Pin QFN package θ Total Power Dissipa- tion ψ Thermal characteristic JT 1 parameter - junction to top center of the 56-Pin QFN package ψ )/P. ...
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... Integrated 10/100 Fast Ethernet Transceiver 4.3.2 88E3018 Device 64-Pin QFN package Symb ol Para meter θ Thermal resistance - JA junction to ambient of the 64-Pin QFN package θ Total Power Dissipa- tion ψ Thermal characteristic JT 1 parameter - junction to top center of the 64-Pin QFN package ψ ...
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Current Consumption Note The following current consumption numbers are shown when external supplies are used. If internal regulators are used, the current consumption will not change; however, the power consumed inside the package will increase. 4.4.1 Current Consumption AVDD ...
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... Integrated 10/100 Fast Ethernet Transceiver Note The following current consumption numbers are shown when external supplies are used. If internal regulators are used, the current consumption will not change; however, the power consumed inside the package will increase. 4.4.3 Current Consumption DVDD ...
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DC Operating Conditions 4.5.1 Non-MAC Interface Digital Pins (Over full range of values listed in the Recommended Operating Conditions unless otherwise specified ...
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... Integrated 10/100 Fast Ethernet Transceiver 4.5.2 Stub-Series Transceiver Logic (SSTL_2) Figure 16: SSTL_2 Termination Circuit Note This circuit can be used if termination is required. This circuit can also be used unterminated if the interconnect is short. Figure 17: SSTL_2 Input Voltage Levels Doc. No. MV-S103657-00, Rev. C Page 94 Document Classification: Proprietary Information ...
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Table 59: Reference I/O Parameters Param eter Desc ription VDDQ Output Supply Voltage VREF Input Reference Voltage VTT Termination Voltage VIH(dc) DC Input Logic High VIL(dc) DC Input Logic Low VIH(ac) AC Input Logic High VIL(ac) AC Input Logic Low ...
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... Integrated 10/100 Fast Ethernet Transceiver 4.5.3 IEEE DC Transceiver Parameters IEEE tests are typically based on template and cannot simply be specified by a number. For an exact description of the template and the test conditions, refer to the IEEE specifications. • 10BASE-T IEEE 802.3 Clause 14 • 100BASE-TX ANSI X3.263-1995 ...
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AC Electrical Specifications 4.6.1 Reset and Configuration Timing (Over full range of values listed in the Recommended Operating Conditions unless otherwise specified) Symbol Parameter T Power up to hardware PU_ de-asserted RESET T Number of valid REFCLK SU_CLK cycles ...
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... Integrated 10/100 Fast Ethernet Transceiver 4.6.2 XTAL_IN Input Clock Timing (Over full range of values listed in the Recommended Operating Conditions unless otherwise specified) Sy mbo l Pa rame ter T XTAL_IN Period P_XTAL_IN T XTAL_IN High time H_XTAL_IN T XTAL_IN Low time L_XTAL_IN T XTAL_IN Rise R_XTAL_IN T XTAL_IN Fall ...
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MII Interface Timing 4.7.1 100 Mbps MII Transmit Timing - Non Source Synchronous (Over full range of values listed in the Recommended Operating Conditions unless otherwise specified) Symbol Parameter T MII Setup Time SU_MII_ TX_CLK T MII Hold Time ...
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... Integrated 10/100 Fast Ethernet Transceiver 4.7.3 100 Mbps MII Transmit Timing - Source Synchronous (Over full range of values listed in the Recommended Operating Conditions unless otherwise specified) Symbol Parameter T MII Setup Time SU_MII_ TX_CLK T MII Hold Time HD_MII_ TX_CLK T TX_CLK High H_MII_ TX_CLK ...
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Mbps MII Receive Timing (Over full range of values listed in the Recommended Operating Conditions unless otherwise specified MII Output to Clock SU_MII_ RX_CLK T MII Clock to ...
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... Integrated 10/100 Fast Ethernet Transceiver 4.8 RGMII Interface Timing 4.8.1 RGMII Transmit Timing 4.8.1.1 100 Mbps RGMII Transmit Timing (Over full range of values listed in the Recommended Operating Conditions unless otherwise specified) Symbol Parameter T RGMII Setup Time SU_RGMII_ TX_CLK T RGMII Hold Time HD_RGMII_ TX_CLK ...
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RGMII Receive Timing 4.8.2.1 Register 28.11: (Over full range of values listed in the Recommended Operating Conditions unless otherwise specified All speeds skew Figure ...
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... Integrated 10/100 Fast Ethernet Transceiver 10 Mbps RGMII Receive Timing (Over full range of values listed in the Recommended Operating Conditions unless otherwise specified) Symbol Para meter T RGMII Output to Clock SU_RGMII_ RX_CLK T RGMII Clock to Output HD_RGMII_ RX_CLK T RX_CLK High H_RGMII_ RX_CLK T RX_CLK Low ...
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Latency Timing 4.9.1 MII to 100BASE-TX Transmit Latency Timing (Over full range of values listed in the Recommended Operating Conditions unless otherwise specified) Symbol Para meter T 100BASE-TX TX_CTRL AS_TXCTRL_ Asserted to COL Asserted COL_100 T 100BASE-TX TX_CTRL AS_TXCTRL_ ...
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... Integrated 10/100 Fast Ethernet Transceiver Figure 25: MII to 10/100 Transmit Latency Timing TX_CLK TX_CTRL T AS_TXCTRL_COL COL 100 10 T AS_TXCTRL_MDI Note The collision (COL) diagram assumes that the device was already receiving data when transmission started. In half-duplex mode this will cause a collision. Compare this figure with Doc ...
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MII Receive Latency Timing (Over full range of values listed in the Recommended Operating Conditions unless otherwise specified) Symbol Parameter T 100BASE-TX MDI start of AS_MDI_ Packet to CRS Asserted CRS_100 T 100BASE-TX MDI start of AS_MDI_ ...
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... Integrated 10/100 Fast Ethernet Transceiver Figure 26: 10/100 to MII Receive Latency Timing /J/ /K/ 100 10 PREAMBLE CRS COL RX_CTRL T AS_MDI_CRS T AS_MDI_COL T AS_MDI_RXCTRL Note This diagram assumes that the device was already transmitting data when data has started to be received from the link partner. In half-duplex mode this will cause a collision. Compare this figure with Doc ...
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RGMII to 100BASE-TX Transmit Latency Timing (Over full range of values listed in the Recommended Operating Conditions unless otherwise specified 100BASE-TX TX_CTRL AS_TXC_ Asserted to ...
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... Integrated 10/100 Fast Ethernet Transceiver 4.9.7 100BASE-TX to RGMII Receive Latency Timing (Over full range of values listed in the Recommended Operating Conditions unless otherwise specified 100BASE-TX MDI start of AS_MDI_ Packet to RX_CTRL RXC_100 Asserted T 100BASE-TX MDI /T/ to ...
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Serial Management Timing (Over full range of values listed in the Recommended Operating Conditions unless otherwise specified) Symbol Pa rame MDC to MDIO (Output) DLY_MDIO Delay Time T MDIO (Input) to MDC SU_ MDIO Setup Time ...
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... Integrated 10/100 Fast Ethernet Transceiver 4.11 JTAG Timing (Over full range of values listed in the Recommended Operating Conditions unless otherwise specified) Symbol TCK Period P_TCK T TCK High H_TCK T TCK Low L_TCK T TDI, TMS to TCK Setup Time SU_TDI T TDI, TMS to TCK Hold Time ...
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... Section 5. Package Mechanical Dimensions 5.1 88E3015 Package Mechanical Dimensions Figure 31: 88E3015 56-pin QFN package D Ø 1.0mm "B" 0. "A" e Copyright © 2006 Marvell October 26, 2006, Advance Document Classification: Proprietary Information 88E3015 Package Mechanical Dimensions L DETAIL : B SEATING PLANE (All dimensions in mm.) ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 60: Dimensions of the 56-pin QFN Package Table 61: 56-Pin QFN Mechanical Dimensions θ aaa bbb chamfer Doc. No. MV-S103657-00, Rev. C Page 114 Document Classification: Proprietary Information ...
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Package Mechanical Dimensions Figure 32: 88E3018 64-pin QFN package D 1.0mm aaa C ''B'' 0. Copyright © 2006 Marvell October 26, 2006, Advance Document Classification: Proprietary Information 88E3018 Package Mechanical ...
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... Integrated 10/100 Fast Ethernet Transceiver Table 62: 64-Pin QFN Mechanical Dimensions θ aaa bbb chamfer Doc. No. MV-S103657-00, Rev. C Page 116 Document Classification: Proprietary Information ...
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... Section 6. Application Examples 6.1 10BASE-T/100BASE-TX Circuit Application Figure 33: 10BASE-T/100BASE-TX Circuit Application 88E3015/ 88E3018 MDIP[0] Ω 49.9 MDIN[0] 2.5V RSET Ω 2.5V MDIP[1] MDIN[1] Ω Ω 49.9 49.9 μ F 0.01 Copyright © 2006 Marvell October 26, 2006, Advance Document Classification: Proprietary Information 10BASE-T/100BASE-TX Circuit Application Transformer μ ...
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... Integrated 10/100 Fast Ethernet Transceiver 6.2 FX Interface to 3.3V Fiber Transceiver Figure 34: FX Interface to 3.3V Fiber Transceiver Terminate at fiber inputs Terminate at 88E3015/ TBD -- To be determined by the application of the fiber module. Doc. No. MV-S103657-00, Rev. C Page 118 Document Classification: Proprietary Information 3.3V TBD TBD 0.01 uF 0.01 uF TBD TBD 174 3 ...
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Transmitter - Receiver Diagram Figure 35: Transmitter - Receiver Diagram OFF 3.3V Ω Ω 174 i Sink 3 174i Ω 1.62V ...
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... Integrated 10/100 Fast Ethernet Transceiver 6.4 88E3018 to 88E3015 Backplane Connection - 100BASE-FX Interface Figure 36: 88E3018 to 88E3015 Backplane Connection - 100BASE-FX Interface Ω Ω 88E3018 Ω Ω 174 2.5V or 3.3V SIGDET Doc. No. MV-S103657-00, Rev. C Page 120 Document Classification: Proprietary Information 3.3V 3.3V Ω Ω ...
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Another Vendor’s PHY - 100BASE-FX Interface through a Backplane 6.5 88E3018 to Another Vendor’s PHY - 100BASE-FX Inter- face through a Backplane Figure 37: 88E3018 to Another Vendor’s PHY - 100BASE-FX Interface through a Backplane TBD RXP RXN ...
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... MDIP[0] MDIN[0] 2.5V or 3.3V SIGDET Doc. No. MV-S103657-00, Rev. C Page 122 Document Classification: Proprietary Information 3.3V Ω 69 Ω 174 3.3V Ω Ω 174 174 2.5V or 3.3V CONFIDENTIAL MDIP[0] MDIN[0] 88E3015/ 88E3018 Ω MDIP[1] MDIN[1] Ω SIGDET Copyright © 2006 Marvell October 26, 2006, Advance ...
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... Section 7. Order Information 7.1 Ordering Part Numbers and Package Markings Figure 39 shows the ordering part numbering scheme for the 88E3015/88E3018 device. Contact Marvell or sales representatives for complete ordering information. Figure 39: Sample Part Number 88E301x Part Number 88E3015 88E3018 Custom Code Package Code ...
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... Integrated 10/100 Fast Ethernet Transceiver Figure example of the package marking and pin 1 location for the 88E3015 56-pin QFN commercial RoHS 5/6 compliant package. Figure 40: 88E3015 56-pin QFN Commercial RoHS 5/6 Compliant Package Marking and Pin 1 Location Country of origin (Contained in the mold ID or marked as the last line on the package ...
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Figure example of the package marking and pin 1 location for the 88E3018 64-pin QFN industrial RoHS 6/6 compliant package. Figure 42: 88E3018 64-pin QFN Industrial RoHS 6/6 Compliant Package Marking and Pin 1 Location Country of ...
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... Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 www.marvell.com Worldwide Corporate Offices Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Marvell Asia Pte, Ltd. 151 Lorong Chuan, #02-05 New Tech Park, Singapore 556741 Tel: 65 ...