MIC2342 MICREL [Micrel Semiconductor], MIC2342 Datasheet - Page 6

• Manufacturer Part Number: MIC2342
• Manufacturer: MICREL [Micrel Semiconductor]

Pin Description (cont.)
Micrel, Inc.
June 2008
Pin Number
14
23
11
26
15
22
44
43
45
42
35
31
2
6
CFILTERA
CFILTERB
/PWRGDA
/PWRGDB
3VGATEA
3VGATEB
Pin Name
AUXENA
AUXENB
VSTBYA
VSTBYB
VAUXA
VAUXB
ONA
ONB
Pin Function
3V Gate Drive Outputs [A/B]: Each pin connects to the gate of an external N-
channel power MOSFET. During power-up, the C
the external MOSFETs are connected to a 25µA current source. This controls
the value of dv/dt seen at the source of the MOSFETs, and hence the current
flowing into the 3V load capacitance.
During current limit events, the voltage at this pin is adjusted to maintain
constant current through the FET for a period of t
shorter). Whenever an overcurrent, thermal shutdown, or input undervoltage
fault condition occurs, the corresponding 3VGATE pin for the affected slot is
pulled down to AGND to turn OFF the external MOSFET.
3.3V Standby Supply Voltage: Required to support the PCI Express VAUX
output. Additionally, all internal logic circuitry operates on VSTBY[A/B]. An
internal UVLO circuit prevents turn-on of the external 3.3VAUX supply until the
voltage at the VSTBY[A/B] pins is higher than the V
Both pins must be externally connected together at the MIC2342 controller.
3.3VAUX[A/B] Outputs to PCI Express Card Slots: These outputs connect the
3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal 0.4-Ω
MOSFETs. These outputs are current limited and protected against short-circuit
faults.
Main +12VOUT[A/B] and +3.3VOUT[A/B] Enable Inputs: These level-sensitive
digital inputs are each internally connected with pull-up resistors to VSTBY[A]
and are used to enable or disable the MAIN[A/B] (+3.3V and +12V) outputs.
Applying a high-to-low transition on ON[A/B] for at least 200ns (t
resets the +12V and/or +3.3V fault latches for the affected slot and de-asserts
the /FAULT_MAIN[A/B] output signals. The +12V and/or the +3.3V electronic
circuit breakers are reset once the /FAULT_MAIN[A/B] output signals are de-
asserted.
VAUX[A/B] Enable Inputs: These level-sensitive digital inputs are each internally
connected with pull-up resistors to VSTBY[A] and are used to enable or disable
the VAUX[A/B] outputs. Applying a high-to-low transition on AUXEN[A/B] for at
least 200ns (t
and de-asserts the /FAULT_AUX[A/B] output signals. The VAUX[A/B] electronic
circuit breakers are reset once the /FAULT_AUX[A/B] output signals are de-
asserted.
Overcurrent Filter Capacitor [A/B]: Capacitors connected between these pins
and AGND set the duration of t
(OC) detector circuits. t
current limit before its circuit breaker is tripped. To configure the controller to use
its internal digital filter delay timer, CFILTER[A/B] pins shall be connected to
AGND. If the overcurrent filter times out during an AUX fault condition to
shutdown the AUX output, the MAIN outputs of the corresponding slot will also
be shutdown (See the “Output Signals’ Timing Responses” in Figure 9 in the
Functional Description section).
/PWRGD[A/B] are open-drain, asserted active-LOW digital outputs that are
normally connected by an external 10kΩ pull-up resistor (each) to VSTBY. Each
output signal is asserted when inputs signals ON[A/B] and AUXEN[A/B] have
been enabled, each output voltage has crossed its respective Power-is-Good
output threshold (V
fault conditions exist . Please consult the /PWRGD[A/B] and the
/DLY_PWRGD[A/B] state diagrams in the Applications Information section for
more detail.
LPW
) after a fault resets the VAUX fault latches for the affected slot
UVTH(12V)
6
FLT
is the amount of time for which a slot remains in
, V
UVTH(3V)
FLT
, the response time of the primary overcurrent
, and V
UVTH(VAUX)
FLT
GATE
UVLO(STBY)
or t
threshold voltages), and no
(if used) and the C
DFLT
(whichever is
threshold voltage.
LPW
) after a fault
MIC2342/2342R
GS
M9999-062008-B
of