CS4223_03 CIRRUS [Cirrus Logic], CS4223_03 Datasheet
CS4223_03
Related parts for CS4223_03
CS4223_03 Summary of contents
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Audio Codec with Volume Control Features 105 dB Dynamic Range A/D Converters 105 dB Dynamic Range D/A Converters 110 dB DAC Signal-to-Noise Ratio (EIAJ) Analog Volume Control (CS4224 only) Differential Inputs / Outputs On-chip Anti-aliasing and Output ...
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TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4 SPECIFIED OPERATING CONDITIONS ................................................................................. 4 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4 ANALOG CHARACTERISTICS ................................................................................................ 5 SWITCHING CHARACTERISTICS .......................................................................................... 8 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (CS4224) ..................... 9 SWITCHING CHARACTERISTICS ...
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Serial Data Output Format (DOF).................................................................................. 17 5.5.4 Serial Data Input Format (DIF) ...................................................................................... 17 5.6 Converter Status Report (Read Only) (address 06h) ....................................................... 18 5.6.1 Left and Right Channel Acceptance Bit (ACCR-ACCL) ................................................ 18 5.6.2 Left and Right Channel ...
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LIST OF TABLES Table 1. Example Volume Settings ............................................................................................... 16 Table 2. Common Clock Frequencies ........................................................................................... 19 Table 3. Digital Interface Format - DIF1 and DIF0 ....................................................................... 20 Table 4. De-emphasis Control....................................................................................................... 20 Table 5. Common Clock Frequencies ........................................................................................... 21 ...
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CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T = 25°C.) A SPECIFIED OPERATING CONDITIONS (AGND, DGND ...
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ANALOG CHARACTERISTICS Bandwidth kHz; Local components as shown in Figures 4 and 5.) Parameter Analog Input Characteristics Total Harmonic Distortion Dynamic Range Total Harmonic Distortion + Noise Interchannel Isolation Interchannel Gain Mismatch Offset Error with ...
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ANALOG CHARACTERISTICS (CONTINUED) Parameter Analog Output Characteristics - Minimum Attenuation, 10 kΩ, 100 pF load; unless otherwise specified. Signal-to-Noise, Idle-Channel Noise (CS4224 only) DAC muted, A-weighted Dynamic Range DAC not muted, A-weighted DAC not muted, unweighted Total Harmonic Distortion Total ...
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DIGITAL CHARACTERISTICS Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage -2 Low-level Output Voltage 2 Input Leakage Current Output Leakage Current High Impedance Digital Outputs 8 Symbol Min ...
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SWITCHING CHARACTERISTICS Parameter Audio ADC’s and DAC’s Sample Rate XTI Frequency XTI Pulse Width High XTI Pulse Width Low XTI Jitter Tolerance RST Low Time SCLK falling edge to SDOUT output valid LRCK edge to MSB valid SDIN setup time ...
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SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (CS4224) (Inputs: Logic 0 = DGND, Logic 1 = VD; C Parameter SPI Mode (SPI/I2C = 0) CCLK Clock Frequency RST rising edge to CS falling CCLK edge to CS falling CS ...
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SWITCHING CHARACTERISTICS - CONTROL PORT - I (Inputs: Logic 0 = DGND, Logic 1 = VD; C Parameter 2 ® Mode (SPI/I2C = 1) SCL Clock Frequency RST rising edge to Start Bus Free Time between transmissions Start ...
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TYPICAL CONNECTION DIAGRAM — CS4223 Ferrite Bead +5V Supply + 1 µF 150Ω 20 2.2 nF 150Ω 19 150Ω 17 2.2 nF 150Ω Mode Selection 500 Ω ...
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TYPICAL CONNECTION DIAGRAM — CS4224 Ferrite Bead +5V Supply + 1 µF 150 Ω 20 2.2 nF 150 Ω 19 150 Ω 17 2.2 nF 150 Ω Microcontroller 500 Ω ...
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REGISTER QUICK REFERENCE - CS4224 Addr Function 7 0h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved default 0 1h ADC Control PDN default 0 2h DAC Control Reserved default 0 3h-4h Output Attenuator ATT7 Level default 0 ...
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REGISTER DESCRIPTIONS - CS4224 Note: All registers are read/write in I 5.1 ADC Control (address 01h PDN HPDR HPDL 0 0 5.1.1 POWER DOWN ADC (PDN) Default = Disabled 1 - Enabled Function: The ...
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CLOCKING ERROR (CLKE) (READ ONLY) Default = error 1 - Error 5.2 DAC Control (address 02h Reserved MUTC MUTR 0 0 5.2.1 MUTE ON CONSECUTIVE ZEROS (MUTC) Default = Disabled ...
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SOFT RAMP STEP RATE (RMP) Default = step per 8 LRCK step per 4 LRCK step per 16 LRCK step per 32 LRCK's Function: The rate ...
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DSP Port Mode (address 05h Reserved DEM1 DEM0 0 0 5.5.1 DE-EMPHASIS CONTROL (DEM) Default = 44.1 kHz de-emphasis setting kHz de-emphasis setting kHz de-emphasis setting 11 - ...
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Converter Status Report (Read Only) (address 06h ACCR ACCL LVR2 0 0 5.6.1 LEFT AND RIGHT CHANNEL ACCEPTANCE BIT (ACCR-ACCL) Default = Requested setting valid 1 - New setting loaded Function: The ACCR and ...
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PIN DESCRIPTIONS — CS4223 NC 1,14,15 Connect - These pins are not connected internally and should be tied to DGND to mini- mize noise coupling. XTI, XTO 2,3 Crystal Connections (Input/Output) - Input and output connections for ...
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SDIN 9 Serial Data Input (Input) - Two's complement MSB-first serial data is input on this pin. The required relationship between the left/right clock, serial clock and serial data is defined by the DIF1-0 pins. The options are detailed in ...
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PIN DESCRIPTIONS — CS4224 NC 1,14,15 Connect - These pins are not connected internally and should be tied to DGND to mini- mize noise coupling. XTI, XTO 2,3 Crystal Connections (Input/Output) - Input and output connections for ...
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SDOUT 8 Serial Data Output (Output) - Two's complement MSB-first serial data is output on this pin. The required relationship between the left/right clock, serial clock and serial data is defined by the DSP Port Mode (05h) register. The options ...
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APPLICATIONS 8.1 Overview The CS4223 is a stand-alone device controlled through dedicated pins. The CS4224 is controlled with an external microcontroller using the serial control port. 8.2 Grounding and Power Supply Decoupling As with any high resolution converter, the ...
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Control Port Interface (CS4224 only) The control port is used to load all the internal set- tings. The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference prob- lems, ...
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Memory Address Pointer (MAP Reserved Reserved INCR 0 0 8.9.1 AUTO-INCREMENT CONTROL (INCR) Default = Disabled 1 - Enabled 8.9.2 REGISTER POINTER (MAP) Default = 000 CS CCLK CDIN SDA 001000 SCL Start 26 ...
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L eft Master 24-bit data XTI=256, 384, 512 Fs ...
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clocks Master Right-justified, 20-bit ...
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Gain µ - Figure 15. De-emphasis Curve DS290F1 Figure 14. 2- and 3-Pole Butterworth Filters µs F2 Frequency Figure 16. Hybrid Analog/Digital Attenuation CS4223 CS4224 Analog Digital 0 Signal ...
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ADC/DAC FILTER RESPONSE Figure 17. ADC Filter Response Figure 19. ADC Transition Band Figure 21. DAC Passband Ripple 30 CS4223 CS4224 Figure 18. ADC Passband Ripple Figure 20. DAC Filter Response Figure 22. DAC Transition Band DS290F1 ...
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DEFINITIONS Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with ...
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DIMENSIONS 28L SSOP PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.002 A2 0.064 b 0.009 D 0.390 E 0.291 E1 0.197 e 0.022 L 0.025 ∝ 0° Notes: 1. “D” and ...
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Notes • ...
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