CS4270_06 CIRRUS [Cirrus Logic], CS4270_06 Datasheet
CS4270_06
Related parts for CS4270_06
CS4270_06 Summary of contents
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Stereo Audio CODEC D/A Features High Performance – 105 dB Dynamic Range – -95 dB THD+N Selectable Serial Audio Interface Formats – Left-Justified up to 24-bit – I² 24-bit – Right-Justified 16-, and 24-Bit Control ...
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Stand-Alone Mode Feature Set System Features – Serial Audio Port Master or Slave Operation – Single-, Double-, or Quad-Speed Operation D/A Features – Auto-Mute on Static Samples 44.1 kHz 50/15 µs De-emphasis Available – – Selectable Serial Audio Interface Formats ...
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TABLE OF CONTENTS 1. PIN DESCRIPTIONS - SOFTWARE MODE ........................................................................................... 6 2. PIN DESCRIPTIONS - STAND-ALONE MODE ..................................................................................... 7 3. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 8 4. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 9 SPECIFIED OPERATING CONDITIONS ............................................................................................... 9 ABSOLUTE MAXIMUM RATINGS ......................................................................................................... ...
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Power Control - Address 02h ........................................................................................................ 35 8.2.1 Freeze (Bit 7) ......................................................................................................................... 35 8.2.2 PDN_ADC (Bit 5) ................................................................................................................... 35 8.2.3 PDN_DAC (Bit 1) ................................................................................................................... 35 8.2.4 Power Down (Bit 0) ............................................................................................................... 35 8.3 Mode Control - Address 03h ......................................................................................................... ...
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Figure 19. CS4270 Recommended Analog Output Filter .......................................................................... 30 Figure 20. Suggested Active-Low Mute Circuit ......................................................................................... 31 Figure 21. Control Port Timing, SPI Mode ................................................................................................ 32 Figure 22. Control Port Timing, I²C Mode ................................................................................................. 33 Figure 23. De-Emphasis Curve ................................................................................................................. ...
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PIN DESCRIPTIONS - SOFTWARE MODE SDIN LRCK MCLK SCLK DGND SDOUT VLC SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN Pin Name # SDIN 1 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Left Right Clock (Input/Output) - ...
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PIN DESCRIPTIONS - STAND-ALONE MODE SDIN LRCK MCLK SCLK DGND SDOUT I²S/LJ MDIV1 Pin Name # SDIN 1 Serial Audio Data Input (Input) - Input for two’s complement serial audio data. Left Right Clock (Input/Output) - Determines which channel, ...
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TYPICAL CONNECTION DIAGRAM 47 µF 0.1 µF 10 µF 0.1 µF Analog Input Network (see Figures 12 & 13) Power Down and Mode Settings (Control Port Ω 2 kΩ +1 ...
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CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T = 25°C.) A SPECIFIED OPERATING CONDITIONS (AGND = 0 V; all voltages ...
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DAC ANALOG CHARACTERISTICS - COMMERCIAL GRADE (Full-Scale Output Sine Wave, 997 Hz (see Figure 2). Measurement Bandwidth kHz, unless otherwise specified.) Parameter Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit ...
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DAC ANALOG CHARACTERISTICS - ALL MODES Parameter Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Output Full Scale Output Voltage Max DC Current draw from AOUTA or AOUTB Max AC-Load Resistance (see Figure Max Load Capacitance (see Figure ...
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DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam- ple rate by multiplying the given characteristic by Fs.) (See Parameter Single-Speed Mode ...
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ADC ANALOG CHARACTERISTICS - COMMERCIAL GRADE Measurement bandwidth kHz unless otherwise specified. Dynamic Performance for Commercial Grade Single-Speed Mode Dynamic Range Total Harmonic Distortion + Noise Double-Speed Mode Dynamic Range 40 kHz bandwidth unweighted Total ...
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ADC ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE Measurement Bandwidth kHz unless otherwise specified. Dynamic Performance for Automotive Grade Single-Speed Mode Dynamic Range Total Harmonic Distortion + Noise Double-Speed Mode Dynamic Range 40 kHz bandwidth unweighted Total ...
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ADC DIGITAL FILTER CHARACTERISTICS (Measurement Bandwidth kHz unless otherwise specified) Parameter Single-Speed Mode Passband (-0.1 dB) Passband Ripple Stopband Stopband Attenuation Group Delay Double-Speed Mode Passband (-0.1 dB) Passband Ripple Stopband Stopband Attenuation Group Delay ...
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DC ELECTRICAL CHARACTERISTICS (T = 25° C; AGND=DGND=0, all voltages with respect to ground; MLCK=12.288 MHz; Master Mode) A Parameter Power Supply Power Supply Current (Normal Operation) Power Supply Current (Power-Down Mode) (Note 14) Power Consumption ...
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SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = AGND = 0 V; Logic "1" = VD, C Parameter Sample Rate MCLK Specifications MCLK Frequency (Note 17) MCLK Duty Cycle Master Mode LRCK Duty Cycle SCLK Period (Note 18) SCLK ...
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LRCK output t mslr SCLK output MSB SDOUT Figure 4. Master Mode, Left-Justified SAI LRCK output t mslr SCLK output MSB SDOUT Figure 6. Master Mode, I²S SAI SCLK SDIN Figure 8. Master and Slave Mode SDIN vrs. SCLK 18 ...
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Left Channel LRCK SCLK SDATA - MSB Figure 9. Format 0, Left-Justified up to 24-Bit Data Left Channel LRCK SCLK SDINx - MSB LRCK Channel A - Left ...
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SWITCHING CHARACTERISTICS - I²C MODE CONTROL PORT (Inputs: logic 0 = DGND, logic 1 = VLC) Parameter I²C Mode SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock ...
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SWITCHING CHARACTERISTICS - SPI (Inputs: logic 0 = DGND, logic 1 = VLC) Parameter SPI Mode CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge ...
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APPLICATIONS 5.1 Stand-Alone Mode 5.1.1 Recommended Power-Up Sequence Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable also recommended that reset be enabled if the ...
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Clock Ratio Selection Depending on whether the CS4270 is in Master or Slave Mode, different MCLK/LRCK and SCLK/LRCK ratios may be used. These ratios are shown in the MCLK/LRCK Single-Speed Double-Speed Quad-Speed MCLK/LRCK Single-Speed Double-Speed Quad-Speed 5.1.5 Interpolation Filter ...
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Mode Selection & De-Emphasis The sample rate, Fs, can be adjusted from 4 kHz to 216 kHz and De-emphasis, optimized for 44.1 kHz, is available in Single-Speed Mode. In Stand-Alone Master Mode, the CS4270 must be set to the ...
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System Clocking The CS4270 will operate at sampling frequencies from 4 kHz to 216 kHz. This range is divided into three speed modes as shown in 5.2.4 Clock Ratio Selection In Control Port Master Mode, the user must configure ...
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Double-Speed 256 384 512 64 96 Quad-Speed 128 192 256 Table 5. Clock Ratios - Control Port Mode (Continued) 5.2.5 Internal Digital Loopback In Control Port Mode, the CS4270 supports an internal digital loopback mode in which the ...
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De-Emphasis One de-emphasis mode is available via the Control Port and is optimized for 44.1 kHz sampling rate. 5.2.9 Oversampling Modes The CS4270 operates in one of three oversampling modes based on the input sample rate. Mode selec- tion ...
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Analog Connections 5.4.1 Input Connections The analog modulator samples the input at 6.144 MHz.The digital filter will reject signals within the stop- band of the filter. However, there is no rejection for input signals which are multiples of the ...
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Figure 17. A/D Dynamic Range vrs. Input Source Resistance Attenuation: The required attenuation factor depends on the magnitude of the input signal. For the full-scale input voltage equals 1 Vrms. The full-scale input voltage scales with ...
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Analog Input 2 kΩ Figure 18. CS4270 Example Analog Input Network 5.4.2 Output Connections The analog output filter present in the CS4270 is a switched-capacitor filter followed by a continuous time low pass filter. Its response, combined with that of ...
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AOUTx CS4270 MUTEx 5.6 Synchronization of Multiple Devices In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS4270’s ...
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CONTROL PORT INTERFACE The Control Port is used to load all the internal settings of the CS4270. The operation of the Control Port may be completely asynchronous to the audio sample rate. However, to avoid potential interference problems, the ...
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I²C Mode In I²C Mode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in partial chip address and should ...
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REGISTER QUICK REFERENCE This table shows the register names and their associated default values. Addr Function 7 01h ID id<3> id<2> 1 02h Power Freeze Reserved PDN_ADC Control 0 03h Funct Mode Reserved Reserved 0 04h ADC HPF ADC ...
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REGISTER DESCRIPTION ** All registers are read/write in I²C Mode and SPI Mode, unless otherwise noted** 8.1 Chip ID - Address 01h 7 6 id<3> id<2> id<1> Function: This register is Read-Only. Bits 7 through 4 are the part ...
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Mode Control - Address 03h 7 6 FM_&_M/S_ Reserved Reserved Mode1 8.3.1 ADC Functional Mode & Master / Slave Mode (Bits 5:4) Function: In Control Port Master Mode, the user must configure the CS4270 Speed Mode with these bits. ...
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ADC HPF Freeze B (Bit 6) Function: When this bit is set, the internal high-pass filter for the selected channel will be disabled.The current DC offset value will be frozen and continuously subtracted from the conversion result. Pass Filter ...
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Transition Control - Address 05h 7 6 DAC Single soft_dac zc_dac Volume 8.5.1 DAC Single Volume (Bit 7) Function: The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Volume Control Bytes when ...
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De-Emphasis Control (Bit 0) Function: Implementation of the standard 50/15 µs digital de-emphasis filter on the DAC output requires reconfigu- ration of the digital filter to maintain the proper filter response for 44.1 kHz sample rate. the filter response. ...
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DAC Channel A Volume Control - Address 07h 7 6 dacA dacA dacA vol<7> vol<6> vol<5> Function: See Section 8.8 DAC Channel B Volume Control - Address 8.8 DAC Channel B Volume Control - Address 08h 7 6 dacB ...
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FILTER PLOTS Figure 24. DAC Single-Speed Stopband Rejection -10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency (normalized to Fs) Figure 26. DAC Single-Speed Transition Band (detail) Figure 28. ...
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Frequency (normalized to Fs) Figure 30. DAC Double-Speed Transition Band (detail) ...
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Frequency (norm alized to Fs) Figure 36. ADC Single-Speed Stopband Rejection ...
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Frequency (norm alized to Fs) Figure 42. ADC Double-Speed Transition Band (detail) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 ...
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DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a ...
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DIMENSIONS 24L TSSOP (4.4 mm BODY) PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.00197 0.00394 A2 0.03150 0.0394 b 0.00748 0.00965 D 0.30338 BSC 0.30732 BSC 0.31126 BSC E 0.24822 0.25216 ...
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INFORMATION Product Description 24-Bit 192 kHz Stereo CS4270 Audio CODEC 24-Bit 192 kHz Stereo CS4270 Audio CODEC CDB4270 CS4270 Evaluation Board 13.REVISION HISTORY Release A1 Initial Release DS686PP1 Package Pb-Free Grade 24-TSSOP YES Commercial -10° to +70° C 24-TSSOP ...
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Release – Update Release after B0 chip validation – Changed value of A/D shunt capacitor from 2200 pF to 220 pF in – Added “single ended input” to Features” on page 1 – Added “3 core ...
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Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest to you IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full ...