CS44600-DQZ CIRRUS [Cirrus Logic], CS44600-DQZ Datasheet - Page 77

• Manufacturer Part Number: CS44600-DQZ
• Description: 6-Channel Digital Amplifier Controller
• Manufacturer: CIRRUS [Cirrus Logic]

DS633PP1
12.REVISION HISTORY
Release
PP1
A1
A2
A3
September 2004 Updated lead-free device ordering information
October 2004
May 2004
May 2005
Date
-Updated
-Updated
-Updated
-Updated
-Updated
-Updated
-Updated
-Updated
-Updated
-Updated
-Updated
-Updated
-Updated
-Updated
-Updated
-Updated
-Updated
-Updated
-Updated
-Updated
-Updated
-Updated
-Updated
-Corrected
-Corrected
-Corrected
-Updated
(addresses 18h, 1Ah, 1Ch, 1Eh, 20h, 22h),” on page 60
-Updated
(addresses 19h, 1Bh, 1Dh, 1Fh, 21h, 23h),” on page 61
-Updated
-Updated
1st Advance Release
-Updated
-Updated
-Correcte
-Corrected
-Corrected
-Corrected
-Corrected
-Corrected
-Updated
-Updated
-Corrected
-Updated
“Features” on page 1
“External Crystal operating frequency” on page 11
“Typical Full-Bridge Connection Diagram” on page 22
“Typical Half-Bridge Connection Diagram” on page 23
Section 4.2 "Feature Set Summary" on page 22
“FsOut Domain Clocking” on page 24
“Sample Rate Converter” on page 31
“PWM Engines” on page 32
Table 4, “Typical PWM Switch Rate Settings,” on page 33
Section 4.5.8 "Modulator" on page 33
Section 4.5.10 on page 34
Section 4.6.1 "SPI Mode" on page 35
Section 4.6.2 "I²C Mode" on page 36
Section 5. "Power Supply, Grounding, and PCB layout" on page 38
Section 5.1 "Reset and Power-Up" on page 41
Section 5.1.1 "PWM PopGuard® Transient Control" on page 41
Section 5.1.2 "Recommended Power-Up Sequence" on page 41
Section 5.1.3 "Recommended PSR Calibration Sequence" on page 42
Section 5.1.4 "Recommended Power-Down Sequence" on page 43
Section 6. "Register Quick Reference" on page 44
Section 7.5.2 "AM Frequency Hopping (AM_FREQ_HOP)" on page 51
Section 7.6 "Ramp Configuration (address 05h)" on page 52
Section 7.7.3 on page 53
Table 7.18, “Chnl XX Load Compensation Filter - Coarse Adjust
Table 7.19, “Chnl XX Load Compensation Filter - Fine Adjust
Section 7.26 "GPIO Pin Level/Edge Trigger (address 2Eh)" on page 65
Section 7.29 "PWM Configuration Register (address 31h)" on page 66
“Features” on page 1
“Ordering Information” on page 2
“Typical Full-Bridge Connection Diagram” on page 22
“Typical Half-Bridge Connection Diagram” on page 23
Section 7.5.2 "AM Frequency Hopping (AM_FREQ_HOP)" on page 51
“Power Supply Current” on page 9
Table 7, “Master Fractional Volume Settings,” on page 56
Table 9, “Channel Fractional Volume Settings,” on page 58
Table 11, “Limiter Release Rate Settings,” on page 60
“High-Level Input Voltage” on page 9
“Low-Level Input Voltage” on page 9
“High-Level Output Voltage at Io = -2 mA” on page 9
“Low-Level Output Voltage at Io = 2 mA” on page 9
“Digital Filter Response (Note 12)” on page 11
Figure 13 on page 23
Table 19. Revision History
Changes
CS44600
77