CS4923 CIRRUS [Cirrus Logic], CS4923 Datasheet
CS4923
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CS4923 Summary of contents
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... Description The CS4923/4/5/6/7 family of multi-channel digital audio decoders, with the exception of the CS4929 as the ® only stereo digital audio decoder. The CS4923/4/5/6 are , designed for Dolby Digital and MPEG-2 Stereo decoding. In addition the CS4925 adds MPEG-2 multi-channel decoding capability and the CS4926 provides DTS decoding. The CS4927 is an MPEG-2 multi-channel decoder and the CS4928 is a DTS multi-channel decoder ...
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... SWITCHING CHARACTERISTICS—DIGITAL AUDIO INPUT................................................ 16 SWITCHING CHARACTERISTICS—DIGITAL AUDIO OUTPUT............................................ 18 2. FAMILY OVERVIEW .............................................................................................................. 20 2.1 Multi-channel Decoder Family of Parts ............................................................................ 21 2.2 Document Strategy .......................................................................................................... 21 2.2.1 Hardware Documentation ............................................................................... 22 2.2.2 CS4923/4/5/6/7/8/9 Application Code User’s Guides ..................................... 22 2.3 Using the CS4923/4/5/6/7/8/9 .......................................................................................... 22 3. TYPICAL CONNECTION DIAGRAMS ................................................................................... 23 3.1 Multiplexed Pins ............................................................................................................... 23 3.2 Termination Requirements ............................................................................................... 24 3.3 Phase Locked Loop Filter ................................................................................................ 24 4. POWER .................................................................................................................................. 31 4 ...
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... Table 6. Motorola Parallel Host Mode Pin Assignments ................................................................ 36 Table 7. SPI Serial Mode Pin Assignments.................................................................................... 36 2 Table Serial Mode Pin Assignments .................................................................................... 39 Table 9. Memory Interface Pins...................................................................................................... 41 Table 10. Digital Audio Input Port................................................................................................... 46 Table 11. Compressed Data Input Port .......................................................................................... 46 Table 12. Digital Audio Output Port ................................................................................................ 47 Table 13. MCLK/SCLK Master Mode Ratios .................................................................................. 47 DS262F2 CS4923/4/5/6/7/8/9 3 ...
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... VA ||VA| – |VD IND T Amax T stg Symbol Positive digital VD Positive analog VA ||VA| – |VD Symbol Symbol Digital operating: VD[3:1] Analog operating: VA CS4923/4/5/6/7/8/9 Min Max –0.3 3.63 –0.3 3. –0.3 5.5 –55 125 –65 150 Min Typ Max 3.13 3.3 3.47 3.13 3 Min ...
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... All bidirectional pins high-Z after RESET low Configuration bits setup before RESET high Configuration bits hold after RESET high PSEL, ABOOT All Bidirectional DS262F2 Symbol T RESET RD, WR, Outputs T rst2z T rstl Figure 1. RESET Timing CS4923/4/5/6/7/8 pF)z L Min Max T 100 - rstl rst2z ...
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... C; VA 3.3 V 5%; Inputs: Logic 0 = DGND, Logic Parameter Serial compressed data clock CMPCLK period CMPDAT setup before CMPCLK high CMPDAT hold after CMPCLK high CMPCLK CMPDAT 6 Symbol T cmpclk T cmpsu T cmphld T cmpsu T cmpclk Figure 2. Serial Compressed Data Timing CS4923/4/5/6/7/8 pF) L Min Max cmphld Unit DS262F2 ...
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... Figure 3. CLKIN with CLKSEL = VSS = PLL Enable CLKIN Figure 4. CLKIN with CLKSEL = VD = PLL Bypass DS262F2 Symbol T clki T clkih T clkil T clke T clkeh T clkel T T clkih clkil T clki T T clkeh clkel T clke CS4923/4/5/6/7/8 pF) L Min Max Unit 20 3800 ...
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... DCLK == CLKIN after boot Internal Clock Mode: DCLK == 10MHz before and during boot, i.e. DCLK == 100ns DCLK == 60 MHz after boot, i.e. DCLK == 16.7ns (this speed may depend on CLKIN, please see CS4923/4/5/6/7/8/9 Hardware User’s Guide for more information) 2. This specification is characterized but not production tested. 8 CS4923/4/5/6/7/8/9 ® ...
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... DATA7:0 T ias CS T icdr WR RD A1:0 T DATA7:0 T ias CS T icdw RD WR DS262F2 iah T idhr T idd T idis T T irpw ird Figure 5. Intel Parallel Host Mode Read Cycle iah T idhw T idsu T T iwpw iwd Figure 6. Intel Parallel Host Mode Write Cycle CS4923/4/5/6/7/8/9 T irdtw T iwtrd 9 ...
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... DCLK == CLKIN after boot Internal Clock Mode: DCLK == 10MHz before and during boot, i.e. DCLK == 100ns DCLK == 60 MHz after boot, i.e. DCLK == 16.7ns (this speed may depend on CLKIN, please see CS4923/4/5/6/7/8/9 Hardware Users Guide for more information) 4. This specification is characterized but not production tested. 10 CS4923/4/5/6/7/8/9 ® ...
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... Figure 7. Motorola Parallel Host Mode Read Cycle A1:0 T mas DATA7:0 CS R/W DS Figure 8. Motorola Parallel Host Mode Write Cycle DS262F2 T mah T mdhr T mdd T T mcdr mdis T T mrpw mrd T mah T T mdsu mdhw T T mwpw mcdw T mrwsu CS4923/4/5/6/7/8/9 T mrwhld T mrdtw T mrwhld T T mwd mwtrd 11 ...
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... This time is by design and not tested. 12 (Note 5) (Note 11) (Note 11) (Note 6) (Note 7) (Note 8) (Note 8) (Note 9, 11) (Note 11) indicates the maximum speed of the hardware. The system designer should be CS4923/4/5/6/7/8 pF) L Symbol Min Max Units f - 2000 kHz sck t ...
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CS t css t scl SCCLK t sch SCDIN t cdisu t cdih SCDOUT INTREQ R/W MSB MSB t scdov t scdov t scrh Figure ...
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... SCDIO setup time to SCCLK rising SCDIO hold time from SCCLK falling Rise time of SCCLK Fall time of SCCLK Time from SCCLK falling to CS4923/4/5/6/7/8/9 ACK Time from SCCLK falling to SCDIO valid during read operation Time from SCCLK rising to INTREQ rising Hold time for INTREQ from SCCLK rising ...
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A6 A5 SCDIO t buf t sud 1 0 SCCLK t hdst t low t hdd t high INTREQ A0 ACK MSB R/W t scsdv sca 2 Figure 10. ...
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... SDATAN1(2) hold time after SCLKN1(2) transition Notes: 19. Master mode timing specifications are characterized, not production tested. 20. Master mode is defined as the CS4923 driving LRCLKN1(2) and SCLKN1(2). Master or Slave mode can be programmed. 21. This timing parameter is defined from the non-active edge of SCLKN1(2). The active edge of SCLKN1(2) is the point at which the data is valid ...
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... Figure 11. Digital Audio Input, Data and Clock Timing DS262F2 MASTER MODE SCLKN1 SCLKN2 T lrds LRCLKN1 LRCLKN2 T T sdsum sdhm SDATAN1 SDATAN2 SLAVE MODE SCLKN1 SCLKN2 T lrts LRCLKN1 LRCLKN2 T T sdsus sdhs SDATAN1 SDATAN2 CS4923/4/5/6/7/8/9 T sclki T sclki T stlr 17 ...
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... Notes: 24. MCLK can be an input or an output. These specifications apply for both cases. 25. Master mode timing specifications are characterized, not production tested. 26. Master mode is defined as the CS4923 driving both SCLK and LRCLK. When MCLK is an input divided to produce SCLK and LRCLK. ...
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... MCLK (Input) SCLK (Output) MCLK (Output) SCLK (Output) SCLK LRCLK AUDATA2:0 SCLK LRCLK AUDATA2:0 Figure 12. Digital Audio Output, Data and Clock Timing DS262F2 T mclk T sdmi T mclk T sdmo MASTER MODE T sclk T lrds T adsm SLAVE MODE T sclk T lrts T stlr T adss CS4923/4/5/6/7/8/9 19 ...
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... The important differentiation is the format in which the data will be received by the CS4923/4/5/6/7/8/9. In systems where A/V synchronization is required from the CS4923/4/5/6/7/8/9, the incoming data is typically PES encoded outboard decoder application the data typically comes in the IEC61937 format (as specified by the DVD consortium) ...
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... Multi-channel Decoder Family of Parts TM CS4923 - Dolby Digital Audio Decoder. The CS4923 is the original member of the family and is intended to be used if only Dolby Digital decoding is required. For Dolby Digital, post processing includes bass management, delays and Dolby Pro Logic decoding. Separate downloads can also be used to support stereo to 5 ...
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... DTS code including bass management and DTS processing features. AN123 - Surround User’s Guide for the CS4923/4/5/6/7/8. This code covers the different Stereo PCM to surround effects processing code. Optional appendices are available that document Crystal Original Surround, Circle Surround and Logic 7 ...
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... It is highly suggested that the system designer take advantage of the PLL and pull CLKSEL low. 3.1 Multiplexed Pins The CS4923/4/5/6/7/8/9 family of digital signal processors (DSPs) incorporate a large amount of flexibility into a 44 pin package. Because of the high degree of integration, many of these pins are internally multiplexed to serve multiple purposes ...
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... GPIO pins and unused inputs. 3.3 Phase Locked Loop Filter The internal phase locked loop (PLL) of the CS4923/4/5/6/7/8/9 requires an external filter for successful operation. The topology of this filter and component values are shown in the typical connection diagrams. Care should be taken when ...
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... Figure 13 Control CS4923/4/5/6/7/8/9 +3.3VA + 0 NOTE: Only AUDATA0 connection applies for the CS4929 ...
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... EMAD[7:0] 2 Figure 14 Control with External Memory CS4923/4/5/6/7/8/9 +3.3VA + + 0 NOTE: Only AUDATA0 connection applies for the CS4929 ...
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... Figure 15. SPI Control CS4923/4/5/6/7/8/9 +3.3VA + 0 NOTE: Only AUDATA0 connection applies for the CS4929 ...
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... DATA DATA DATA DAT CS4923/4/5/6/7/8 DATA OSCILLATOR ...
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... Figure 17. Intel Parallel Control Mode CS4923/4/5/6/7/8/9 +3.3VA + 0 NOTE: Only AUDATA0 connection applies for the CS4929 ...
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... Figure 18. Motorola Parallel Control Mode CS4923/4/5/6/7/8/9 +3.3VA + 0 NOTE: Only AUDATA0 connection applies for the CS4929 ...
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... CS492X power supplies require 3.3 volts, 5 volt signals can be applied to the inputs without damaging the part. (VD1/DGND, The I/O pads for Revision B of the CS4923/4/5/6 are not 5 volt tolerant. Input levels for revision B of capacitors. The the CS4923/4/5/6 should be no greater than 3.3 ...
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... CLOCKING Revision D of the CS4923/4/5/6/7/8/9 also incorporates a programmable phase locked loop (PLL) clock synthesizer. The PLL takes an input reference clock and produces all the internal clocks required to run the internal DSP and to provide master mode timing to the audio input/output peripherals. The clock manager also includes a ...
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... User’s Guide and the application code user’s guides. 6.1 Boot and Control Mode Overview 8-bit Motorola Regardless of which communication mode is used, 8-bit Intel the CS4923/4/5/6/7/8/9 must be booted and loaded 2 Serial I C with code at run time. The general sequence from a Serial SPI ...
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... Intel parallel host mode is accomplished with CS, RD, WR, A[1:0], and DATA[7:0]. Table 4 shows the pin name, pin description and pin number of 34 each signal on the CS4923/4/5/6/7/8/9. RD and WR have no effect when CS is held high. When the DSP writes a byte to the HOSTMSG register, the HOUTRDY bit in the CONTROL register is set to indicate that there is data to be read ...
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... The host writes compressed data to the DSP input buffer at this address. (Write only) DS262F2 HOSTMSG4 HOSTMSG3 MFC MFB PCMDATA4 PCMDATA3 CMPDATA4 CMPDATA3 Table 5. Parallel Input/Output Registers CS4923/4/5/6/7/8 HOSTMSG2 HOSTMSG1 HOSTMSG0 2 1 HINBSY HOUTRDY Reserved 2 1 PCMDATA2 PCMDATA1 PCMDATA0 2 1 CMPDATA2 CMPDATA1 CMPDATA0 0 0 ...
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... CS, SCCLK, SCDIN, SCDOUT and INTREQ. Table 7 shows the pin name, pin description and pin number of each signal on the CS4923/4/5/6/7/8/ active low chip select and must be held low for writes to and reads from the part. SCCLK is an input to the CS492X that clocks data in and out of the device on its rising edge ...
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... SCCLK does not occur the final byte will be lost and successful communication will not be possible. 6.3.2 SPI Read The CS4923/4/5/6/7/8/9 will always indicate that it has data to be read by asserting the INTREQ line low. The host must recognize the request and start a read transaction with the CS492X. The same protocol will be used whether reading a byte or multiple bytes ...
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... INTREQ Notes: 1. INTREQ is guaranteed to stay low until the rising edge of SCCLK for the second to last bit of the last byte to be transferred out of the CS4923/4/5/6/7/8/9 2. INTREQ is guaranteed to stay high until the next rising edge of SCCLK at which point it may go low again if there is new data to be read. The condition of INTREQ going low at this point ...
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... SCCLK, SCDIO and INTREQ. Table 8 shows the mnemonic, pin name, and pin number of each signal on the CS4923/4/5/6/7/8/9. SCCLK is an input to the CS492X that clocks data in and out of the device on its rising edge. It should be noted that the timing specifications for SCCLK are more stringent than ...
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... Note 1 Notes: 1. The ACK for the address byte is driven by the CS4923/4/5/6/7/8/9. 2. The ACKs for the data bytes being read from the CS4923/4/5/6/7/8/9 should be driven by the host. 3. INTREQ is guaranteed to stay low until the rising edge of SCCLK for last bit of the last byte to be transferred out of the CS4923/4/5/6/7/8/9 4 ...
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... C, the EMAD2 EMAD1 EMAD0 * - These pins must be configured appropriately to select a serial host communication mode for the CS4923/4/5/6/7/8/9 at the rising edge of RESET The external memory address is capable of addressing between 64 kilobytes and 16 megabytes through bit addressing scheme. The address comes from the DSP writing two or three initial bytes of address consecutively on EMAD[7:0] ...
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... Please see section 2, Serial Communication for R2 R4 more d etails. Figure 21. External Memory Interface MA15:8 Figure 22. Run-Time Memory Access CS4923/4/5/6/7/8/9 ADDR[7: A[7:0] ADDR[15:8] ADDR[15: 64K MA7:0 ...
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... The higher order address byte simply shifts out of the memory latch and is discarded. If desired, a three latch to interface CS4923/4/5/7/9 but it is not necessary. For more information about autoboot and for a thorough description of different external memory 2 C serial architectures, reference the CS4923/4/5/6/7/8/9 Hardware User’ ...
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... DIGITAL INPUT & OUTPUT The CS4923/4/5/6/7/8/9 supports a wide variety of data input and output mechanisms through various input and output ports. Hardware availability is entirely dependent on whether the software application code being used supports the required mode. This data sheet presents most of the modes available with the CS4923/4/5/6/7/8/9 hardware ...
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... MSB Figure 25. Left Justified Format Left MSB LSB Figure 26. Right Justified LSB MSB LSB MSB M Clocks M Clocks Per Channel Per Channel Figure 27. Multi-Channel Format (M == 20) CS4923/4/5/6/7/8/9 Right LSB Right LSB MSB Right MSB LSB LSB MSB LSB MSB LSB M Clocks M Clocks ...
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... Pin Number special format in which only clock (CMPCLK) and 22 data (CMPDAT) are used to deliver compressed 25 data to the CS4923/4/5/6/7/8/9 (i.e. no frame clock 26 or LRCLK). A third line, CMPREQ, is used to request more data from the host indicator that the CS492X internal FIFO is low on data and ...
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... In parallel host mode, the CS4923/4/5/6/7/8/9 can accept PCM data written through the byte-wide host interface to address 10b (A1 high, A0 low). In this mode, there is a close connection between the CS4923/4/5/6/7/8/9 application code and the host processor that is delivering the PCM data. The PCMRST bit of the CONTROL register provides ...
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... IEC61937 fully IEC60958 compliant this output would need to be buffered through an RS422 device or an optocoupler as its outputs are only CMOS. CS4923/4/5/6/7/8/9 Hardware User’s Guide and an application code user’s guide to determine if this pin is supported by the download code being used. CS4923/4/5/6/7/8/9 Please ...
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... CS4923- 44-pin PLCC Top View CS4923/4/5/6/7/8/9 MCLK SCLK LRCLK AUDATA0 AUDATA1 AUDATA2 DC DD RESET AGND VA FILT1 FILT2 CLKSEL CLKIN CMPREQ, LRCLKN2 CMPCLK, SCLKN2 CMPDAT, SDATAN2 LRCLKN1 SCLKN1, STCCLK2 ...
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... VD), this input is connected to the DSP clock. INPUT CLKSEL—DSP Clock Select: Pin 31 This pin selects the clock mode of the CS4923/4/5/6/7/8/9. When CLKSEL is low, CLKIN is connected to the internal PLL from which all internal clocks are derived. When CLKSEL is high CLKIN is connected to the DSP clock. INPUT DATA7, EMAD7, GPIO7— ...
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... RESET—Master Reset Input: Pin 36 Asynchronous active-low master reset input. Reset should be low at power-up to initialize the CS4923/4/5/6/7/8/9 and to guarantee that the device is not active during initial power-on stabilization periods. At the rising edge of reset the host interface mode is selected contingent on the state of the RD, WR and PSEL pins. Additionally, an autoboot sequence can be initiated if a serial control mode is selected and ABOOT is held low ...
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... OUTPUT MCLK—Audio Master Clock: Pin 44 Bidirectional master audio clock. MCLK can be an output from the CS4923/4/5/6/7/8/9 that provides an oversampled audio-output clock at either 128 Fs, 256 Fs, or 512 Fs. MCLK can be an input at 128 Fs, 256 Fs, 384 Fs, or 512 Fs. MCLK is used to derive SCLK and LRCLK when SCLK and LRCLK are driven by the CS492X. BIDIRECTIONAL - Default: INPUT SCLK— ...
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... SDATAN2 can be sampled with either edge of SCLKN2, depending on how SCLKN2 has been configured. Similarly CMPDAT is the compressed data input pin when the CDI is configured for bursty delivery. When in this mode, the CS4923/4/5/6/7/8/9 internal PLL is driven by the clock recovered from the incoming data stream. INPUT DC— ...
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... E 0.685 E1 0.650 E2 0.590 e 0.040 INCHES MAX 0.180 0.120 0.021 0.695 0.656 0.630 0.695 0.656 0.630 0.060 CS4923/4/5/6/7/8/9 e D2/ MILLIMETERS MIN MAX 4.043 4.572 2.205 3.048 0.319 0.533 16.783 17.653 15.925 16.662 14.455 16.002 16.783 17.653 15.925 16.662 14 ...
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Notes • ...
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