SN74LS196 MOTOROLA [Motorola, Inc], SN74LS196 Datasheet - Page 5

• Manufacturer Part Number: SN74LS196
• Description: 4-STAGE PRESETTABLE RIPPLE COUNTERS
• Manufacturer: MOTOROLA [Motorola, Inc]

AC CHARACTERISTICS
AC SETUP REQUIREMENTS
DEFINITIONS OF TERMS
SETUP TIME (t s ) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from HIGH to LOW in order to be recog-
nized and transferred to the outputs.
HOLD TIME (t h ) — is defined as the minimum time following
the clock transition from HIGH to LOW that the logic level must
be maintained at the input in order to ensure continued recog-
f MAX
t PLH
t PHL
t PLH
t PHL
t PLH
t PHL
t PLH
t PHL
t PLH
t PHL
t PLH
t PHL
t PHL
t W
t W
t W
t W
t s
t s
t h
t h
t rec
S
S
Symbol
S
S
Symbol
b l
b l
b l
b l
Maximum Clock Frequency
CP 0 Input to
Q 0 Output
CP 1 Input to
Q 1 Output
CP 1 Input to
Q 2 Output
CP 1 Input to
Q 3 Output
Data to Output
PL Input to
Any Output
MR Input to Any Output
CP 0 Pulse Width
CP 1 Pulse Width
PL Pulse Width
MR Pulse Width
Data Input Setup Time — HIGH
Data Input Setup Time — LOW
Data Hold Time — HIGH
Data Hold Time — LOW
Recovery Time
P
P
Parameter
P
P
Parameter
(T A = 25 C)
(T A = 25 C)
SN54/74LS196 SN54/74LS197
Min
FAST AND LS TTL DATA
Min
30
20
30
20
15
10
15
10
10
30
LS196
LS196
Typ
Typ
8.0
40
13
16
22
38
41
12
30
20
29
27
30
34
5-5
Max
Max
15
20
24
33
57
62
18
45
30
44
41
45
51
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from HIGH to
LOW and still be recognized.
RECOVERY TIME (t rec ) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from HIGH to LOW in order to recognize and transfer
LOW Data to the Q outputs.
Limits
Limits
Min
Min
30
20
30
20
15
10
15
10
10
30
LS197
LS197
Typ
8.0
Typ
40
14
12
23
34
42
55
63
18
29
26
30
34
Max
Max
15
21
19
35
51
63
78
95
27
44
39
45
51
MHz
U i
U i
Unit
U i
U i
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
T
Test Conditions
T
T
Test Conditions
V
V
V
V CC = 5.0 V
V
V
V
V
V CC = 5.0 V
C L = 15 pF
CC
C
C
C
C
di i
di i
5 0 V
5 0 V
5 0 V
di i
di i
5 0 V
5 0 V
5 0 V
5 0 V