SM8578 Nippon_Precision_Circuits America, SM8578 Datasheet - Page 10

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SM8578

Manufacturer Part Number
SM8578
Description
Real-time Clock IC
Manufacturer
Nippon_Precision_Circuits America
Datasheet

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Control Register 2 (Register F)
This register controls the clock timing frequency divider.
I
I
I
I
*1. The automatic correction function operates if the HOLD bit is set for less than 1 second.
*2. Normal operation for source clocks other than 1/60Hz (1 minute).
*3. Normal operation for 4096Hz source clock only.
*4. Normal operation for 32768Hz source clock only.
Address
RESET
TEST bit: NPC Test Bit
This bit should be set to “0” when power is applied and when writing to register F.
RESET bit
When this bit is set to “1”, the 2kHz to 1Hz frequency divider counters are reset and clock timing stops.
After “1” data is written, test mode is cancelled by writing “0” data or by setting the CE input LOW.
It is not affected by the state of any other bits.
HOLD bit
When this bit is set to “1”, the seconds digit increment operation is disabled.
However, if an increment operation occurs when this bit is “1” and the bit is subsequently set to “0” within 1
second, the automatic correction function forces a 1-second correction.
Therefore, it is recommended that the HOLD bit should be used for less than 1 second.
Functional operation table
The function of the RESET and HOLD bits is shown in the following table.
F
0
0
1
1
Bit
HOLD
Bit7
0
1
0
1
*
TEST
Bit6
Clock timing
Operating
Stopped
Stopped
*1
Bit5
*
RESET
Timer interrupt output
Bit4
Operating
*2
*3
*3
HOLD
Bit3
SM8578BV
Function
Bit2
Alarm interrupt output
*
Operating
Stopped
Stopped
Stopped
Bit1
*
NIPPON PRECISION CIRCUITS INC.—10
Bit0
*
Arbitrary frequency
Operating
Operating
output
*4
*4

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