LP3907SQ-JXQX NSC [National Semiconductor], LP3907SQ-JXQX Datasheet - Page 27

• Manufacturer Part Number: LP3907SQ-JXQX
• Description: Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface
• Manufacturer: NSC [National Semiconductor]

TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledged related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the ac-
knowledge clock pulse. The receiver must pull down the SDA
line during the 9th clock pulse, signifying acknowledgement.
A receiver which has been addressed must generate an ac-
knowledgement (“ACK”) after each byte has been received.
After the START condition, the
dress. This address is seven bits long followed by an eighth
w = write (SDA = “0”)
r = read )SDA = “1”)
acl = aclmpw;edge )SDA pulled down by either master or slave)
rs = repeated start
id = LP3907 chip address: 0x60
When a READ function is to be accomplished, a WRITE func-
tion must precede the READ function, as shown in the Read
Cycle waveform.
2
C master sends a chip ad-
I
2
I
I
C Chip Address
2
2
C Write Cycle
C Read Cycle
27
bit which is a data direction bit (R/W). Please note that ac-
cording to industry
of an 8-bit address is removed, and communication actually
starts with the 7th most significant bit. For the eighth bit (LSB),
a “0” indicates a WRITE and a “1” indicates a READ. The
second byte selects the register to which the data will be writ-
ten. The third byte contains data to write to the selected
register.
LP3907 has a chip address of 60’h, which is factory pro-
grammed.
2
C standards for 7-bit addresses, the MSB
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