ST6200 STMICROELECTRONICS [STMicroelectronics], ST6200 Datasheet - Page 26

• Manufacturer Part Number: ST6200
• Description: 8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST6200C/ST6201C/ST6203C
5.4 INTERRUPTS
The ST6 core may be interrupted by four maska-
ble interrupt sources, in addition to a Non Maska-
ble Interrupt (NMI) source. The interrupt process-
ing flowchart is shown in
Maskable interrupts must be enabled by setting
the GEN bit in the IOR register. However, even if
they are disabled (GEN bit = 0), interrupt events
are latched and may be processed as soon as the
GEN bit is set.
Each source is associated with a specific Interrupt
Vector, located in Program space (see
the vector location, the user must write a Jump in-
Figure 17. Interrupts Block Diagram
26/100
1
PA1..PA3
PB0..PB1
PB3
PB5..PB7
NMI
* Depending on device. See device summary on page 1.
I/O PORT REGISTER
“INPUT WITH INTERRUPT”
CONFIGURATION
CONFIGURATION
I/O PORT REGISTER
“INPUT WITH INTERRUPT”
A/D CONVERTER *
V D D
Figure
TIMER
(ADCR REGISTER)
(TSCR REGISTER)
18.
LATCH
(IOR REGISTER)
EOC BIT
TMZ BIT
EAI BIT
ETI BIT
Table
CLEARED BY H/W
AT START OF VECTOR #0 ROUTINE
AT START OF
VECTOR #1 ROUTINE
CLEARED BY H/W
ESB BIT
7). In
LATCH
BY H/W AT START OF
VECTOR #2 ROUTINE
CLEARED
struction to the associated interrupt service rou-
tine.
When an interrupt source generates an interrupt
request, the PC register is loaded with the address
of the interrupt vector, which then causes a Jump
to the relevant interrupt service routine, thus serv-
icing the interrupt.
Interrupt are triggered by events either on external
pins, or from the on-chip peripherals. Several
events can be ORed on the same interrupt vector.
On-chip peripherals have flag registers to deter-
mine which event triggered the interrupt.
LATCH
(IOR REGISTER)
LES BIT
(IOR REGISTER)
0
1
GEN BIT
VECTOR #0
VECTOR #1
VECTOR #3
VECTOR #4
VECTOR #2
EXIT FROM
STOP/WAIT