ST62E40B STMICROELECTRONICS [STMicroelectronics], ST62E40B Datasheet - Page 54

• Manufacturer Part Number: ST62E40B
• Description: 8-BIT OTP/EPROM MCU WITH LCD DRIVER, EEPROM AND A/D CONVERTER
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST62T40B/E40B
POWER SUPPLY SUPERVISOR (Continued)
4.6.2 PSS Register
The PSS register permits control over the PSS de-
vice. The register can be addressed in the data
space as a RAM location at DAh. This register is
cleared after Reset.
PSS Status Control Register (PSSCR)
Address: DAh - Read/Write
Bit 7 = PIF. Interrupt flag bit. This bit is the interrupt
flag. This bit is set (resp. cleared) as soon as the
equality between nxV
(m+1)xV
Bit 6 = PEI. Interrupt mask bit. This bit is the au-
thorization bit of the interrupt request: – If PEI is
set, the interrupt request can reach the Core. – If
PEI is cleared, the interrupt request cannot reach
the Core.
Bits 5-4 = PDV1, PDV0. Division rate selection bit .
The PDV1/0 bits are used to select the rate of divi-
sion
(m+1)xV
54/72
54
PIF
7
of
PEI
DD
DD
/13) occurs.
/13, according to the hysteresis).
the
PDV1
PSS
V
DD
PDV0
PSS
PSS
voltage
PDR2
PSS
and mxV
PDR1
PSS
(mxV
DD
PDR0
PSS
DD
/13 (resp.
/13
D0
0
or
Table 24. V
bits
Bits 3-1 = PDR2, PDR1, PDR0. Division rate se-
lection bit. The PDR2/1/0 bits are used to inhibit
the PSS device and to select the division rate of
the PSS voltage (nxV
Bit 0 = D0. The PSS comparator output is valid 8
cycle times after the programming of the PDR2/1/0
bits. It is forced to zero in the meantime.
Table 25. P
PDV1
PDR2
0
0
1
1
0
0
0
0
1
1
PDV0
PDR1
SS
0
1
0
1
0
0
1
1
0
0
DD
Voltage division rate selection bits
Voltage division rate selection
3xV
5xV
6xV
7xV
PDR0
mxV
0
1
0
1
0
1
DD
DD
DD
DD
PSS
/13
/13
/13
/13
DD
/13).
PSS State
IDLE
BUSY
BUSY
BUSY
BUSY
BUSY
/13
4xV
6xV
7xV
8xV
(m+ 1) xV
4xV
5xV
6xV
7xV
V
DD
DD
DD
DD
nxV
PSS
/13
/13
/13
/13
PSS
PSS
PSS
PSS
PSS
DD
/13
/13
/13
/13
/13
/13