LT4250H LINER [Linear Technology], LT4250H Datasheet - Page 7

• Manufacturer Part Number: LT4250H
• Description: Negative 48V Hot Swap Controller
• Manufacturer: LINER [Linear Technology]

APPLICATIONS
Hot Circuit Insertion
When circuit boards are inserted into a live – 48V backplane,
the bypass capacitors at the input of the board’s power
module or switching power supply can draw huge tran-
sient currents as they charge up. The transient currents
can cause permanent damage to the board’s components
and cause glitches on the system power supply.
The LT4250 is designed to turn on a board’s supply
voltage in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. The chip
also provides undervoltage, overvoltage and overcurrent
protection while keeping the power module off until its
input voltage is stable and within tolerance.
Power Supply Ramping
The input to the power module on a board is controlled by
placing an external N-channel pass transistor (Q1) in the
power path (Figure 6a, all waveforms are with respect to
the V
detection and R2 prevents high frequency oscillations.
Resistors R4, R5 and R6 provide undervoltage and over-
voltage sensing. By ramping the gate of Q1 up at a slow
rate, the inrush current charging load capacitors C3 and
C4 can be limited to a safe value when the board makes
connection.
Resistor R3 and capacitor C2 act as a feedback network to
accurately control the inrush current. The C2 capacitor can
be calculated with the following equation:
–48V RTN
UV = 38.5V
OV = 71V
C2 = (45 A • C
* DIODES INC. SMAT70A
(SHORT PIN)
– 48V
–48V RTN
*
EE
6.49k
549k
pin of the LT4250). R1 provides current fault
10k
1%
1%
1%
R4
R5
R6
3
2
3
V
UV
OV
EE
1
4
0.02
Figure 6a. Inrush Control Circuitry
5%
L
R1
)/I
U
SENSE
2
INRUSH
5
4
LT4250H
INFORMATION
C1
470nF
25V
GATE
V
U
DD
8
6
IRF530
Q1
R2
10
5%
1k, 5%
R3
100V
15nF
PWRGD
C2
W
DRAIN
7
1
100 F
100V
C3
0.1 F
100V
C4
+
U
4250 F06a
V
GATE IN
V
VI-J30-CY
IN
IN
VICOR
+
–
V
V
OUT
OUT
+
–
+
where C
input capacitance.
Capacitor C1 and resistor R3 prevent Q1 from momen-
tarily turning on when the power pins first make contact.
Without C1 and R3, capacitor C2 would pull the gate of Q1
up to a voltage roughly equal to V
LT4250 could power up and actively pull the gate low. By
placing capacitor C1 in parallel with the gate capacitance
of Q1 and isolating them from C2 using resistor R3 the
problem is solved. The value of C1 is given by:
where V
V
R3 should not exceed a value that produces an
R3 • C2 time-constant of 150 s. A 1k value for R3 will
ensure this for C2 values up to 150nF.
The waveforms are shown in Figure 6b. When the power
pins make contact, they bounce several times. While the
contacts are bouncing, the LT4250 senses an undervoltage
condition and the GATE is immediately pulled low when
the power pins are disconnected.
Once the power pins stop bouncing, the GATE pin starts to
ramp up. When Q1 turns on, the GATE voltage is held
constant by the feedback network of R3 and C2. When the
DRAIN voltage has finished ramping, the GATE pin then
ramps to its final value.
INMAX
C5
100 F
16V
5V
C
1
500mA/DIV
GATE –V
CURRENT
is the maximum operating input voltage.
L
C1 35 • C2 for V
TH
INRUSH
10V/DIV
50V/DIV
50V/DIV
is the total load capacitance = C3 + C4 + module
DRAIN
V
INMAX
is the MOSFET’s minimum gate threshold and
V
EE
EE
V
CONTACT
BOUNCE
CONTACT
Figure 6b. Inrush Control Waveforms
BOUNCE
TH
V
TH
LT4250L/LT4250H
INMAX
C
25ms/DIV
2
EE
= 72V
C
• C2/C
GD
TURN-ON
MODULE
GS(Q1)
MODULE
TURN-ON
4250 F06b
before the
4250lhf
7