LT4256 LINER [Linear Technology], LT4256 Datasheet - Page 14

• Manufacturer Part Number: LT4256
• Description: UV, OV and Reverse Supply Protection Controller Low Operating Current: 125?A
• Manufacturer: LINER [Linear Technology]

LTC4365
Transients During OV Fault
The circuit of Figure 14 was used to display transients
during an overvoltage condition. The nominal input supply
is 24V and it has an overvoltage threshold of 30V. The
parasitic inductance is that of a 1 foot wire (roughly 300nH).
Figure 15 shows the waveforms during an overvoltage
condition at V
inductance and resistance of the wire along with the ca-
pacitance at the V
(TVS, Tranzorb) recommended for applications where
the DC input voltage can exceed 24V and with large V
parasitic inductance. No clamp was used to capture the
waveforms of Figure 15. In order to maintain reverse supply
protection, D1 must be a bi-directional clamp rated for at
least 225W peak pulse power dissipation.
APPLICATIONS INFORMATION
24V
14
V
IN
+
12 INCH WIRE
20V/DIV
20V/DIV
2A/DIV
LENGTH
D1
OPTIONAL
C
1000μF
Figure 14. OV Fault with Large V
GATE
V
IN
OUT
V
Figure 15. Transients During OV Fault When No
Tranzorb (TVS) Is Used
I
IN
IN
IN
. These transients depend on the parasitic
R2
2370k
R1
40.2k
IN
node. D1 is an optional power clamp
R3
100k
M1
V
SHDN
UV
OV
IN
250ns/DIV
LTC4365
SI9945
GATE
GND
60V
FAULT
V
4365 F14
OUT
M2
IN
Inductance
GATE
V
OUT
OV = 30V
+
4365 F15
C
100μF
GND
GND
0A
OUT
V
OUT
9Ω
IN
MOSFET Selection
To protect against a negative voltage at V
N-channel MOSFETs must be configured in a back-to-
back arrangement. Dual N-channel packages are thus the
best choice. The MOSFET is selected based on its power
handling capability, drain and gate breakdown voltages,
and threshold voltage.
The drain to source breakdown voltage must be higher
than the maximum voltage expected between V
V
transients during normal operation or during Hot Swap™,
the external MOSFET must be able to withstand this
transient voltage.
Due to the high impedance nature of the charge pump that
drives the GATE pin, the total leakage on the GATE pin must
be kept low. The gate drive curves of Figure 2 were measured
with a 1μA load on the GATE pin. Therefore, the leakage
on the GATE pin must be no greater than 1μA in order to
match the curves of Figure 2. Higher leakage currents will
result in lower gate drive. The dual N-channel MOSFETs
shown in Table 1 all have a maximum GATE leakage cur-
rent of 100nA. Additionally, Table 1 lists representative
MOSFETs that would work at different values of V
Layout Considerations
The trace length between the V
external MOSFET should be minimized, as well as the
trace length between the GATE pin of the LTC4365 and
the gates of the external MOSFETs.
Place the bypass capacitors at V
to the external MOSFET. Use high frequency ceramic
capacitors in addition to bulk capacitors to mitigate Hot
Swap ringing. Place the high frequency capacitors closest
to the MOSFET. Note that bulk capacitors mitigate ringing
by virtue of their ESR. Ceramic capacitors have low ESR
and can thus ring near their resonant frequency.
OUT
. Note that if an application generates high energy
IN
OUT
pin and the drain of the
as close as possible
IN
, the external
IN
IN
.
and
4365f