ADN2860-EVAL AD [Analog Devices], ADN2860-EVAL Datasheet - Page 5

• Manufacturer Part Number: ADN2860-EVAL
• Description: 3-Channel Digital Potentiometer with Nonvolatile Memory
• Manufacturer: AD [Analog Devices]

ELECTRICAL CHARACTERISTICS
Single Supply: V
Dual Supply: V
Table 2.
Parameter
DYNAMIC CHARACTERISTICS
INTERFACE TIMING CHARACTERISTICS (Apply
to All Parts)
FLASH/EE MEMORY RELIABILITY
1
2
3
4
5
6
7
Typical represents average readings at 25°C, V
All dynamic characteristics use V
Guaranteed by design and not subject to production test.
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
See Figure 2 for the location of measured values.
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +85°C. Typical endurance at 25°C is 700,000 cycles.
Retention lifetime equivalent at junction temperature (T
bandwidth. The highest R value results in the minimum overall power consumption.
derates with junction temperature.
Bandwidth −3 dB
Total Harmonic Distortion
V
Resistor Noise Spectral Density
Digital Crosstalk
Analog Crosstalk
SCL Clock Frequency
t
t
t
t
t
t
t
t
t
t
EEMEM Data Storing Time
EEMEM Data Restoring Time at Power-On
EEMEM Data Restoring Time on Restore
Command or Reset Operation
EEMEM Data Rewritable Time
Endurance
Data Retention
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
R
F
SU;STO
W
Fall Time of Both SDA and SCL Signals
Rise Time of Both SDA and SCL Signals
Settling Time
Bus Free Time between Stop and Start
Low Period of SCL Clock
High Period of SCL Clock
Setup Time for Start Condition
Setup Time for Stop Condition
Hold Time (Repeated Start)
Data Setup Time
Data Hold Time
4, 5
6
DD
DD
7
= +2.25 V or +2.75 V, V
= 3 V to 5.5 V and −40°C < T
DD
2, 3
= 5 V.
DD
= 5 V.
SS
= −2.25 V or −2.75 V, and −40°C < T
J
) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV
A
C
Symbol
BW
THD
t
e
C
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SCL
S
1
2
3
4
5
6
7
8
9
10
EEMEM_STORE
EEMEM_RESTORE1
EEMEM_RESTORE2
EEMEM_REWRITE
< +85°C, unless otherwise noted.
N_WB
T
AT
W
Rev. A | Page 5 of 20
Conditions
V
V
V
V
code = 0x000 to 0x100, R
R
V
adjacent RDAC making full-scale
change.
Signal input at A0 and measure output
at W1, f = 1 kHz.
After this period, the first clock pulse is
generated.
55°C.
DD
A
A
W
AB
A
= 1 V rms, V
= V
= V
= 0.50% error band,
/V
= 25 kΩ/250 kΩ, T
SS
DD
DD
= ±2.5 V, R
, V
, V
B
B
= 0 V,
= 0 V, measure VW with
B
= 0 V, f = 1 kHz.
A
< +85°C, unless otherwise noted.
AB
= 25 kΩ/250 kΩ.
A
AB
= 25°C.
= 25 kΩ/250 kΩ.
Min
1.3
600
1.3
0.6
600
100
600
540
100
Typ
125/12
0.05
4/36
14/45
−80
−72
26
360
360
100
1
Max
400
50
900
300
300
ADN2860
Unit
kHz
%
µs
nV√Hz
dB
dB
kHz
µs
ns
µs
µs
ns
ns
ns
ns
ns
ns
ms
µs
µs
µs
kcycles
years