AD5410ACPZ AD [Analog Devices], AD5410ACPZ Datasheet - Page 17

• Manufacturer Part Number: AD5410ACPZ
• Description: Single Channel, 16-Bit, Serial Input, Current Source DAC
• Manufacturer: AD [Analog Devices]

AD5410/AD5420
THEORY OF OPERATION
The AD5410/AD5420 is a precision digital to current loop
output converter designed to meet the requirements of
industrial process control applications. It provides a high
precision, fully integrated, low cost single-chip solution for
generating current loop outputs. The current ranges available
are; 0 to 20mA, 0 to 24mA and 4 to 20mA, The desired output
configuration is user selectable via the CONTROL register.
ARCHITECTURE
The DAC core architecture of the AD5410/AD5420 consists of
two matched DAC sections. A simplified circuit diagram is
shown in Figure 33. The 4 MSBs of the 12/16-bit data word are
decoded to drive 15 switches, E1 to E15. Each of these switches
connects 1 of 15 matched resistors to either ground or the
reference buffer output. The remaining 8/12 bits of the data-
word drive switches S0 to S11 of a 8/12-bit voltage mode R-2R
ladder network.
V
The voltage output from the DAC core is converted to a current
(see diagram, Figure 34) which is then mirrored to the supply
rail so that the application simply sees a current source output
with respect to ground.
12/16-BIT
REF
DAC
2R
Figure 34. Voltage to Current conversion circuitry
8/12-BIT R-2R LADDER
2R
S0
Figure 33. DAC Ladder Structure
A1
2R
S1
T1
R1
R2
2R
S7/S11
FOUR MSBs DECODED INTO
A2
15 EQUAL SEGMENTS
2R
E1
T2
AV
DD
2R
E2
R3
I
OUT
2R
E15
Rev. PrE | Page 17 of 30
V
OUT
Reference Buffers
The AD5410/AD5420 can operate with either an external or
internal reference. The reference input has an input range of 4 V
to 5 V, 5 V for specified performance. This input voltage is then
buffered before it is applied to the DAC.
SERIAL INTERFACE
The AD5410/AD5420 is controlled over a versatile 3-wire serial
interface that operates at clock rates up to 30 MHz. It is
compatible with SPI®, QSPI™, MICROWIRE™, and DSP
standards.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. Data is clocked in on the rising edge of
SCLK. The input register consists of 8 control bits and 16 data
bits as shown in
Preliminary Technical Data