ASM1832S PULSECORE [PulseCore Semiconductor], ASM1832S Datasheet - Page 4

no-image

ASM1832S

Manufacturer Part Number
ASM1832S
Description
3.3V ?P Power Supply Monitor and Reset Circuit
Manufacturer
PULSECORE [PulseCore Semiconductor]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ASM1832S
Manufacturer:
PULSECORE
Quantity:
3 730
October 2006
rev 1.6
signals. The pushbutton input is debounced and is pulled
HIGH through an internal 40kΩ resistor.
When PBRST is held LOW for the minimum time t
resets become active and remain active for a minimum time
period of 250ms after PBRST returns HIGH.
The debounced input is guaranteed to recognize pulses
greater than 20ms. No external pull-up resistor is required,
since PBRST is pulled HIGH by an internal 40kΩ resistor.
The PBRST can be driven from a TTL or CMOS logic line or
shorted to ground with a mechanical switch.
Watchdog Timer and ST Input
A watchdog timer stops and restarts a microprocessor that is
“hung-up”. The µP must toggle the ST input within a set
period (as selectable through TD input) to verify proper
software execution. If the ST is not toggled low within the
Figure 3: Timing Diagram: Pushbutton Reset
PBRST
RESET
RESET
Figure 4: Application Circuit: Pushbutton Reset
1
2
4
3
GND
PBRST
T
TOL
D
V
ASM1832
t
PDLY
IL
RESET
RESET
V
ST
CC
t
PB
Supply
Voltage
5
6
7
8
Notice: The information in this document is subject to change without notice
3.3V µP Power Supply Monitor and Reset Circuit
RESET
I/O
t
V
RST
IH
µP
PB
V
V
OH
OL
, both
minimum timeout period, reset signals become active. On
power-up after the supply voltage returns to an in-tolerance
condition, the reset signal remains active for 250ms
minimum,
microprocessor to stabilize.
ST Pulses as short as 20ns can be detected.
Timeouts periods of approximately 150ms, 610ms or
1,200ms are selected through the TD pin.
The watchdog timer can not be disabled. It must be strobed
with a high-to-low transition to avoid watchdog timeout and
reset.
Note: ST is ignored whenever a reset is active
Figure 5: Timing Diagram: Strobe Input
Figure 6: Application Circuit: Watchdog Timer
TD Voltage level
RESET
ST
1
2
4
3
Floating
GND
GND
PBRST
T
TOL
V
t
allowing
RST
D
ASM1832
CC
RESET
RESET
V
ST
CC
Valid
Strobe
t
t
Supply
Voltage
6
5
the
7
TD
8
ST
(min)
power
Watchdog Time-out Period
Valid
Strobe
62.5
Min
250
500
RESET
µP
supply
t
TD
ASM1832
(max)
Address
MREQ
(ms)
Nom
1200
Bus
150
610
and
Decoder
Invalid
Strobe
1000
2000
system
Max
250
4 of 9

Related parts for ASM1832S