C504 SIEMENS [Siemens Semiconductor Group], C504 Datasheet - Page 33

• Manufacturer Part Number: C504
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Power Saving Modes
Two power down modes are available, the idle mode and power down mode.
Table 10 gives a general overview of the power saving modes.
Table 10
Power Saving Modes Overview
Mode
Idle mode
Power-Down
Mode
In the power down mode of operation,
be ensured, however, that
is restored to its normal operating level, before the power down mode is terminated.
The idle mode can be terminated by activating any enabled peripheral interrupt or by resetting the
C504. The power down mode can be terminated using an interrupt by a short low pulse at the pin
P3.2/AN4/INT0 or by resetting the C504. If a power saving mode is left through an interrupt, the
microcontroller state (CPU, ports, peripherals) remains preserved. If a power saving mode is left by
a reset operation, the microcontroller state is disturbed and replaced by the reset state of the C504.
Semiconductor Group
– In the idle mode the oscillator of the C504 continues to run, but the CPU is gated off from the
– In the power down mode, the RC oscillator and the on-chip oscillator which operates with the
clock signal. However, the interrupt system, the serial port, the A/D converter, and all timers
with the exception of the watchdog timer are further provided with the clock. The CPU status
is preserved in its entirety: the stack pointer, program counter, program status word,
accumulator, and all other registers maintain their data during idle mode.
XTAL pins is stopped. Therefore all functions of the microcontroller are stopped and only the
contents of the on-chip RAM, XRAM and the SFR's are maintained. The port pins, which are
controlled by their port latches, output the values that are held by their SFR's.
Entering
2-Instruction
Example
ORL PCON, #01H
ORL PCON, #20H
ORL PCON, #02H
ORL PCON, #40H
V
CC
is not reduced before the power down mode is invoked, and that
V
CC
can be reduced to minimize power consumption. It must
Leaving by
Ocurrence of an
interrupt from a
peripheral unit
Hardware Reset
Hardware Reset
Wake-up from power
down
33
Remarks
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock
Oscillator is stopped;
contents of on-chip RAM and
SFR’s are maintained;
C504
V
CC