IR3088AM IRF [International Rectifier], IR3088AM Datasheet
IR3088AM
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IR3088AM Summary of contents
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XPHASE DESCRIPTION The IR3088A Phase IC combined with an IR XPhase implement power solutions for the latest high performance CPUs and ASICs. The “Control” IC provides overall system control and interfaces with any number of “Phase” ICs which each drive ...
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... ORDERING INFORAMATION Device IR3088AMTR * IR3088AM * Samples only ABSOLUTE MAXIMUM RATINGS Operating Junction Temperature……………..150 Storage Temperature Range………………….-65 ESD Rating………………………………………HBM Class 1C JEDEC standard ...
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ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over: 8.4V ≤ ≤ 14V ≤ T ≤ 125 PARAMETER Gate Drivers GATEH Rise Time GATEH Fall Time GATEL Rise Time GATEL Fall Time ...
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PARAMETER Ramp Comparator Input Offset Voltage Hysteresis RMPIN+, RMPIN- Bias Current Propagation Delay PWM Comparator PWM Comparator Input Offset Voltage EAIN & PWMRMP Bias Current Propagation Delay Common Mode Input Range Share Adjust Error Amplifier Input Offset Voltage Input Voltage ...
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PARAMETER General VCC Supply Current VCCL Supply Current VCCH Supply Current BIASIN Bias Current DACIN Bias Current Note 1: Guaranteed by design, but not tested in production PIN DESCRIPTION PIN# PIN SYMBOL PIN DESCRIPTION 1 RMPIN+ Non-inverting input to Ramp ...
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SYSTEM THEORY OF OPERATION TM XPhase Architecture TM The XPhase architecture is designed for multiphase interleaved buck converters which are used in applications requiring small size, design flexibility, low voltage, high current and fast transient response. The architecture can control ...
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PWM Control Method The PWM block diagram of the XPhase trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. An external RC circuit connected to the ...
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VPEAK (5.0V) VPHASE4&5 (4.5V) VPHASE3&6 (3.5V) VPHASE2&7 (2.5V) VPHASE1&8 (1.5V) VVALLEY (1.00V) PWM Operation The PWM comparator is located in the Phase IC. Upon receiving a clock pulse, the PWM latch is set; the PWMRMP voltage begins to increase; the ...
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PHASE IC CLOCK PULSE EAIN PWMRMP VDAC GATEH GATEL STEADY-STATE OPERATION TM Body Braking In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; The ...
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Figure 5. Inductor Current Sensing and Current Sense Amplifier The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled ...
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IR3088A THEORY OF OPERATION Block Diagram The Block diagram of the IR3088A is shown in figure 6, and specific features are discussed in the following sections. RAMP COMPARATOR RMPIN+ CLOCK + PULSE RMPIN- - GENERATOR EAIN SYSTEM BIASIN REFERENCE VOLTAGE ...
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Phase Fault It is possible for multiphase converters to appear to be working correctly with one or more phases not functioning. The output voltage can still be regulated and the full load current may still be delivered. However, the remaining ...
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RVCC QGATE 10 ohm DGATE CVCC RGATE 0.1uF 1nF ENABLE 0.1uF RBBFB 1 21 OSCDS VBIAS RBBDRP VID5 2 20 VID5 BBFB VID0 3 IR3081 19 VID0 EAOUT VID1 4 CONTROL 18 VID1 FB IC VID2 5 17 VID2 ...
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DESIGN PROCEDURES - IR3081 AND IR3088A CHIPSET IR3081 EXTERNAL COMPONENTS Oscillator Resistor Rosc The oscillator of IR3081 generates a triangle waveform to synchronize the phase ICs, and the switching frequency of the each phase converter equals the oscillator frequency, which ...
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SR is proportional to that of VDAC down-slope and is given by Equation (9), where VDAC pin as shown in Figure15 of IR3081 Data Sheet. I SINK = C VDAC SR DOWN = + ...
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MAX = R FB ∗ DRP TM Body Braking Related Resistors R TM The body braking during Dynamic VID can be disabled by connecting BBFB pin to ground. If the feature is ...
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Over Temperature Setting Resistors R The threshold voltage of VRHOT comparator is proportional to the die temperature T the relationship between the die temperature of phase IC and the temperature of the power converter according to the power loss, PCB ...
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If the over temperature setting voltage is higher than the phase delay setting voltage, VBIAS*RA HOTSET pin between R and R PHASEx1 Pre-select R , PHASEx1 ( V HOTSET = R PHASEx PHASEx R PHASEx 3 Bootstrap ...
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∗ optional and may be needed in some applications to reduce the jitter caused by the high frequency ...
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π ∗ ∗ π ∗ π ∗ ∗ ...
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DESIGN EXAMPLE 1 - VRM 10 2U CONVERTER SPECIFICATIONS Input Voltage DAC Voltage: V =1.35 V DAC No Load Output Voltage Offset: V Output Current: I =105 ADC O Maximum Output Current: I =120 ADC OMAX ...
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VDAC Slew Rate Programming Capacitor C From Figure 15 of IR3081 Data Sheet, the sink current of VDAC pin corresponding to 400kHz (R 76uA. Calculate the VDAC down-slope slew-rate programming capacitor from the required down-slope slew rate. − ...
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Body Braking Related Resistors R N/A. The body braking during Dynamic VID is disabled. IR3088A EXTERNAL COMPONENTS PWM Ramp Resistor R and Capacitor C PWMRMP Set PWM ramp magnitude V PWMRMP resistor R , PWMRMP = R PWMRMP ∗ ∗ ...
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Bootstrap Capacitor C BST Choose C =0.1uF BST Decoupling Capacitors for Phase IC and Power Stage Choose C =0.1uF, C =0.1uF VCC VCCL VOLTAGE LOOP COMPENSATION Type II compensation is used for the converter with AL-Polymer output capacitors. Choose the ...
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DESIGN EXAMPLE 2 - EVRD 10 HIGH FREQUENCY ALL-CERAMIC CONVERTER SPECIFICATIONS Input Voltage DAC Voltage: V =1.3 V DAC No Load Output Voltage Offset: V Output Current: I =105 ADC O Maximum Output Current: I =120 ...
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VDAC Slew Rate Programming Capacitor C From Figure 15 of IR3081 Data Sheet, the sink current of VDAC pin corresponding to 800kHz (R 170uA. Calculate the VDAC down-slope slew-rate programming capacitor from the required down-slope slew rate. − ...
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Body Braking Related Resistors R N/A. The body braking during Dynamic VID is disabled. IR3088A EXTERNAL COMPONENTS PWM Ramp Resistor R PWMRMP Set PWM ramp magnitude V PWMRMP resistor R , PWMRMP = R PWMRMP ...
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The over temperature setting voltage of Phases 3 and 4 is higher than the phase delay setting voltage, VBIAS*RA Pre-select R PHASEx. PHASEX1 − ∗ HOTSET PHASE 3 BIAS = R PHASE 32 − ...
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PWMRMP PWMRMP SW PWMRMP = F MI − − − PWMRMP DAC ...
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LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. • Dedicate at least one middle layer for a ground plane, which is ...
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PCB Metal and Component Placement • Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. • Lead land length should be equal to maximum part ...
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Solder Resist • The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non ...
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Stencil Design • The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the ...
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PACKAGE INFORMATION 20L MLPQ ( Body) – θ IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 www.irf.com Page C/W, θ C/W JA ...