LTC1292 LINER [Linear Technology], LTC1292 Datasheet
LTC1292
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LTC1292 Summary of contents
Page 1
... A/D, a differential input, sample-and-hold on the (+) input, and serial I/O. When the LTC1297 is idle between conversions it automatically powers down reducing the supply current typically. The LTC1292 is capable of digitizing signals at a 60kHz rate and with the device’s excellent AC characteristics, it can be used for DSP appli- cations ...
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... Digital Inputs........................................ –0.3V to 12V Digital Outputs .......................... –0. Power Dissipation.............................................. 500mW Operating Temperature Range LTC1292/LTC1297BC, LTC1292/LTC1297CC, LTC1292/LTC1297DC ............................ LTC1292/LTC1297BI, LTC1292/LTC1297CI, LTC1292/LTC1297DI ........................ – Storage Temperature Range ................ – 150 C Lead Temperature (Soldering, 10 sec.)................ 300 VERTER A D ULTIPLEXER CHARACTERISTICS ...
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... 360 4.75V 1.6mA High CC OUT V = 0V, CS High OUT OUT OUT CC LTC1292/LTC1297 LTC1292B/LTC1297B LTC1292C/LTC1297C LTC1292D/LTC1297D MIN TYP MAX UNITS (Note 9) 1.0 MHz 1.5CLK 0.5CLK+5 CLK Cycles 14CLK+2.5 s 14CLK+6 s 160 300 ns 80 150 ns 80 200 ns 130 ns 65 ...
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... C, f CLK 3kHz CLK LTC1297 Supply Current (Power Shutdown) vs Temperature REF = 5V CS HIGH 8 CLK OFF – 50 – 130 AMBIENT TEMPERATURE (°C) UNITS CLK 75 100 125 LTC1292/7 G03 ...
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... AMBIENT TEMPERATURE (°C) LTC1292/7 G08 D Delay Time vs Temperature OUT 250 200 MSB FIRST DATA 150 100 LSB FIRST DATA 50 0 100 125 –50 – AMBIENT TEMPERATURE (°C) LTC1292/7 G11 4 5 LTC1292/7 G06 75 100 125 LTC1292/7 G09 75 100 125 LTC1292/7 G12 5 ...
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... CTIO S # PIN FUNCTION DESCRIPTION 1 CS Chip Select Input A logic low on this input enables the LTC1292/LTC1297. Power shutdown is activated on the LTC1297 when CS is brought high +IN, –IN Analog Inputs These inputs must be free of noise with respect to GND. 4 GND Analog Ground GND should be tied directly to an analog ground plane. ...
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... NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL. dDO 2.4V 0.4V LTC1292/7 TC04 , 2.4V 0.4V LTC1292/7 TC05 ...
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... Voltage Waveforms for serial ports. Bringing CS high resets the LTC1292/LTC1297 for the next data exchange and puts the LTC1297 into its power shutdown mode. Table 1. Microprocessor with Hardware Serial Interfaces Compatible with the LTC1292/LTC1297** PART NUMBER Motorola MC6805S2, S3 ...
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... SPI process. With two 8-bit transfers, the A/D result is read into the MPU (Figure 1). For the LTC1292 the first 8-bit transfer clocks B11 through B8 of the A/D conversion result into the processor. The second 8-bit transfer clocks the remaining bits B7 through B0 into ...
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... LTC1292/7 F02 OPERAND COMMENTS $08 GOES LOW (CS GOES LOW) 6 NOPS FOR TIMING $1029 CHECK SPI STATUS REG $102A LOAD LTC1292 MSBs INTO ACC A $61 STORE MSBs IN $61 $102A LOAD DUMMY DIN INTO SPI, START SCK 6 NOPS FOR TIMING $08,X,$01 D0 GOES HIGH (CS GOES HIGH) ...
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... It can be inserted in the data gathering loop or outside the loop when the data is processed. Interfacing to the Parallel Port of the Intel 8051 Family The Intel 8051 has been chosen to show the interface between the LTC1292/LTC1297 and parallel port microprocessors. The signals CS and CLK are generated ...
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... READ DATA BIT INTO CARRY Sharing the Serial Interface The LTC1292/LTC1297 can share the same two-wire serial interface with other peripheral components or other LTC1292/LTC1297s (Figure 6). In this case, the CS signals decide which LTC1292 is being addressed by the MPU FROM LTC1292/LTC1297 STORED IN 8051 RAM ...
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... LTC1297 LTC1297 2 CHANNELS 2 CHANNELS Figure 6. Several LTC1292/LTC1297s Sharing One 2-Wire Serial Interface use a PC board. The ground pin (Pin 4) should be tied directly to the ground plane with minimum lead length (a low profile socket is fine). Figure 7 shows an example of an ideal LTC1292/LTC1297 ground plane design for a two- sided board ...
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... Input Settling The input capacitor for the LTC1292 is switched onto the “+” input during the sample phase (t 11b and 11c). The sample period can be as short as t ...
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... With the minimum possible sample time suCS R + < 5k and C1 < 20pF will provide adequate SOURCE settling time. In general for both the LTC1292 and LTC1297 keep the product of the total resistance and the total capacitance less than t /9. If this condition can not be SMPL met, then make C1 > ...
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... LT1006 and LT1013 single supply op amps can be made to settle well even with the minimum settling windows of 3.0 s for the LTC1292 or 6.0 s for the LTC1297 (“+” input) and 1 s (“–” input) that occurs at the maximum clock rate of 1MHz. Figures 13 and 14 show examples of both adequate and poor op amp settling ...
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... Figure 11. The sampling interval begins at the rising (e.g the F edge of CS for the LTC1292, and at the falling edge of CS for the LTC1297, and continues until the falling edge of the CLK before the conversion begins. On this falling edge the S&H goes into the hold mode and the conversion begins. ...
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... GND pin. Any voltage drop from the GND pin to the ground plane will cause a gain error. Offset with Reduced V The offset of the LTC1292/LTC1297 has a larger effect on the output code when the A/D is operated with a reduced reference voltage. The offset (which is typi- cally a fixed voltage) becomes a larger fraction of an LSB as the size of the LSB is reduced ...
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... N is the number of bits. Thus the SNR depends on the resolution of the A/D. For an ideal 12-bit A/D the SNR is equal to 74dB. Fast Fourier Transform (FFT) plots of the output spectrum of the LTC1292 are shown in Figures 20a and 20b. The input (f 1kHz and 28kHz with the sampling frequency (f 58 ...
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... The +IN input can accept a resistor value of 1k but the –IN input cannot accept more than 250 when clocked at its maximum clock frequency of 1MHz. If the LTC1292/LTC1297 are clocked at the maximum clock frequency and 250 is not enough to current limit the input source, then the clamp diodes are recommended (Figures 24a and 24b) ...
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... recom CLK D OUT V REF LTC1292/7 F23 5V LTC1292/7 F24a f/32 CLOCK IN 1MHz Figure 26. “Quick Look” Circuit for the LTC1292 LTC1292/LTC1297 without damaging the device. CC 1N4148 DIODES +IN CLK LTC1292 LTC1297 –IN D OUT GND V REF LTC1292/7 F24 Figure 24b ...
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... TO OSCILLOSCOPE “Quick Look” Circuit for the LTC1297 A circuit similar to the one used for the LTC1292 can be used for the LTC1297(Figure 28). A one shot has been generated with NAND gates, a resistor and capacitor to satisfy the setup time t outputs slower clock is used. When CS goes low the one shot is ...
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... LTC Design Note 5). In the opto-isolated interface two signals are generated from one. This allows a two-wire interface to the LTC1292. A long high signal (>1ms) on the CLK IN input allows the 0.1 F capacitor to discharge taking CS high. This resets the A/D for the next conversion. When CLK IN starts toggling, CS goes low and stays there until the next extended CLK IN high time ...
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... LTC1292/LTC1297 PACKAGE DESCRIPTIO CORNER LEADS OPTION (4 PLCS) 0.290 – 0.320 (7.366 – 8.128) 0.045 – 0.068 (1.143 – 1.727) FULL LEAD 0.008 – 0.018 OPTION 0° – 15° (0.203 – 0.457) 0.385 ± 0.025 (9.779 ± 0.635) 0.300 – 0.320 (7.620 – 8.128) 0.009 – ...