LTC1294 LINER [Linear Technology], LTC1294 Datasheet - Page 15

• Manufacturer Part Number: LTC1294
• Description: Single Chip 12-Bit Data Acquisition System
• Manufacturer: LINER [Linear Technology]

D
Motorola SPI (MC68HC11)
The MC68HC11 has been chosen as an example of an MPU
with a dedicated serial port. This MPU transfers data MSB-
first and in 8-bit increments. The D
register starts the SPI process. With three 8-bit transfers,
the A/D result is read into the MPU. The second 8-bit
transfer clocks B11 through B8 of the A/D conversion
result into the processor. The third 8-bit transfer clocks
the remaining bits B7 through B0 into the MPU. The data
is right justified in the two memory locations. ANDing the
second byte with 0D
bits. This operation was not included in the code. It can be
inserted in the data gathering loop or outside the loop
when the data is processed.
CLK
A
OUT
CS
D
IN
TRANSMIT
RECEIVED
PPLICATI
WORD
WORD
MPU
MPU
#62
#63
0
?
O
B7
0
?
D OUT FROM LTC1294 STORED ON MC68HC11 RAM
O
0
?
B6
O
START
U
HEX
BYTE 1
BYTE 1
START
S
1
?
B5
O
SGL/
DIFF
clears the four most significant
SGL
I FOR ATIO
?
U
ODD/
EVEN
B4
O
ODD
?
MSB
SEL
SEL
B11
1
B3
1
?
IN
Hardware and Software Interface to Motorola MC68HC11
word sent to the data
W
SEL
SEL
0
0
?
Data Exchange Between LTC1294 and MC68HC11
B10
B2
UNI
B1
B9
UNI MSBF
LSB
?
B8
B0
U
MSBF
?
BYTE 1
BYTE 2
PS
PS
?
X
ANALOG
0
BYTE 2
BYTE 2
INPUTS
B11
Interfacing to the Parallel Port of the Intel 8051 Family
The Intel 8051 has been chosen to show the interface
between the LTC1293/4/6 and parallel port microproces-
sors. Usually the signals CS, D
on three port lines and the D
port line. This works very well. One can save a line by tying
the D
start bit and D
P1.2. Then P1.2 is reconfigured as an input and the 8051
reads back the 12-bit A/D result over the same data line.
B11
X
B10
B10
IN
X
and D
B9
LTC1293/LTC1294/LTC1296
B9
X
B8
LTC1294
B8
X
OUT
IN
to the LTC1294 over the line connected to
lines together. The 8051 first sends the
B7
D
CLK
OUT
D
CS
IN
DON'T CARE
B7
X
B6
B6
X
OUT
B5
B5
X
IN
BYTE 3 (DUMMY)
B4
signal is read on a fourth
DO
SCK
MOSI
MISO
B4
and CLK are generated
X
BYTE 3
B3
MC68HC11
B3
X
B2
B2
X
B1
B1
X
LTC1293 TD01a
B0
B0
X
15
LTC1293 TD01