LTC1403-1 LINER [Linear Technology], LTC1403-1 Datasheet - Page 13

• Manufacturer Part Number: LTC1403-1
• Description: Serial 12-Bit/14-Bit, 2.8Msps Sampling ADCs with Shutdown
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
Board Layout and Bypassing
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC1403-1/LTC1403A-1, a printed
circuit board with ground plane is required. Layout for the
printed circuit board should ensure that digital and analog
signal lines are separated as much as possible. In particu-
lar, care should be taken not to run any digital track
alongside an analog signal track. If optimum phase match
between the inputs is desired, the length of the two input
wires should be kept matched.
High quality tantalum and ceramic bypass capacitors
should be used at the V
Block Diagram on the first page of this data sheet. For
optimum performance, a 10 F surface mount AVX capaci-
tor with a 0.1 F ceramic is recommended for the V
V
such as Murata GRM219R60J106M may be used. The
capacitors must be located as close to the pins as possible.
The traces connecting the pins and the bypass capacitors
must be kept short and should be made as wide as
possible.
Figure 7 shows the recommended system ground connec-
tions. All analog circuitry grounds should be terminated at
the LTC1403-1/LTC1403A-1 GND (Pins 4, 5, 6 and ex-
posed pad). The ground return from the LTC1403-1/
LTC1403A-1 (Pins 4, 5, 6 and exposed pad) to the power
supply should be low impedance for noise free operation.
REF
Figure 6b. LTC1403-1 6MHz Sine Wave 4096 Point FFT Plot
with the LT1819 Driving the Inputs Differentially
pins. Alternatively, 10 F ceramic chip capacitors
–100
–110
–120
–20
–30
–40
–50
–70
–10
–60
–80
–90
0
0
185k
U
FREQUENCY (Hz)
DD
U
371k
and V
REF
556k
W
pins as shown in the
14031 F06b
741k
U
DD
and
Digital circuitry grounds must be connected to the digital
supply common. In applications where the ADC data
outputs and control signals are connected to a continu-
ously active microprocessor bus, it is possible to get
errors in the conversion results. These errors are due to
feedthrough from the microprocessor to the successive
approximation comparator. The problem can be elimi-
nated by forcing the microprocessor into a Wait state
during conversion or by using three-state buffers to iso-
late the ADC data bus.
POWER-DOWN MODES
Upon power-up, the LTC1403-1/LTC1403A-1 is initialized
to the active state and is ready for conversion. The Nap and
Sleep mode waveforms show the power-down modes for
the LTC1403-1/LTC1403A-1. The SCK and CONV inputs
control the power-down modes (see Timing Diagrams).
Two rising edges at CONV, without any intervening rising
edges at SCK, put the LTC1403-1/LTC1403A-1 in Nap
LTC1403-1/LTC1403A-1
Figure 7. Recommended Layout
13
14031f
14031 F07