LTC1755 LINER [Linear Technology], LTC1755 Datasheet - Page 5

• Manufacturer Part Number: LTC1755
• Description: Smart Card Interface
• Manufacturer: LINER [Linear Technology]

due to the pull-up current source. The I/O pin becomes a
low impedance to ground during the Idle state. It does not
become active until READY goes low indicating that V
stable.
Once READY is low the I/O pin is protected against short
circuits to V
The DATA-I/O channel is bidirectional for half-duplex
transmissions. Its idle state is H-H. Once an L is detected
on one side of the channel the direction of transmission is
established. Specifically, the side which received an L first
is now the input, and the opposite side is the output.
Transmission from the output side back to the input side
is inhibited, thereby preventing a latch condition. Once the
input side releases its L, both sides return to H, and the
channel is now ready for a new L to be transmitted in either
direction. If an L is forced externally on the output side, and
it persists until after the L on the input side is released, this
illegal input will not be transmitted to the input side
because the transmission direction will not have changed.
The direction of transmission can only be established from
the idle (H-H) state and is determined by the first receipt
of an L on either side.
RST (Pin 11): (Output) Level-Shifted Reset Output Pin.
This pin should be connected to the Smart Card RST
contact. The RST pin becomes a low impedance to ground
during the Idle state (see the State Diagram). The reset
channel does not become active until the READY signal
goes low indicating that V
Short-circuit protection is provided on the RST pin by
comparing RST with R
microseconds then the LTC1755 switches to the Alarm
state. This fault checking is only performed after the V
has reached its final value (as indicated by the READY pin).
CLK (Pin 12): (Output) Level-Shifted Clock Output Pin.
This pin should be connected to the Smart Card CLK
contact. The CLK pin becomes a low impedance to ground
during the Idle state (see the State Diagram). The clock
channel does not become active until the READY signal
goes low indicating that V
PIN
U
FUNCTIONS
U
CC
by current limiting to 5mA maximum.
U
IN
. If these signals differ for several
CC
CC
is stable.
is stable.
CC
CC
pin
is
Short-circuit protection is provided on the CLK pin by com-
paring CLK with C
croseconds then the LTC1755 switches to the Alarm state.
This fault checking is only performed after the V
reached its final value (as indicated by the READY pin).
The clock channel is optimized for signal integrity in order
to meet the stringent duty cycle requirements of the EMV
specification. Therefore, to reduce power in low power
applications, clock stop mode is recommended when data
is not being exchanged.
CIN (Pin 13): (Input) Clock Input Pin from the Microcon-
troller. During the Active state this signal appears on the
CLK pin after being level-shifted and buffered.
DV
RIN (Pin 14): (Input) Reset Input Pin from the Microcon-
troller. During the Active state this signal appears on the
RST pin after being level-shifted and buffered.
DV
DATA (Pin 15): (Input/Output) Microcontroller Side Data
I/O Pin. This pin is used for bidirectional data transfer
between the microcontroller and the Smart Card. The
microcontroller data pin must be open drain and must be
able to sink up to 250 A when driving the DATA pin low
due to the pull-up current source. The DATA pin becomes
high impedance during the Idle state or when CS is high
(see the State Diagram). It does not become active until the
READY signal goes low indicating that V
AUX2IN (Pin 16): (Input/Output) Microcontroller Side
Auxiliary I/O pin. This pin is used for bidirectional auxiliary
data transfer between the microcontroller and the Smart
Card. It has the same characteristics as the DATA pin.
AUX1IN (Pin 17): (Input/Output) Microcontroller Side
Auxiliary I/O Pin. This pin is used for bidirectional auxiliary
data transfer between the microcontroller and the Smart
Card. It has the same characteristics as the DATA pin.
C
Terminals. Optimum values for the flying capacitor range
from 0.68 F to 1 F. Best performance is achieved with a
low ESR X7R ceramic capacitor.
+
, C
CC
CC
sets the logic reference level for the C
sets the logic reference level for the R
–
(Pins 18, 19): Charge Pump Flying Capacitor
IN
. If these signals differ for several mi-
CC
LTC1755
is stable.
IN
IN
pin.
pin.
CC
pin has
5