LTC1929 LINER [Linear Technology], LTC1929 Datasheet - Page 16

• Manufacturer Part Number: LTC1929
• Description: 2-Phase, High Efficiency, Synchronous Step-Down Switching Regulator
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
LTC1929
Supplying INTV
from an output-derived source will scale the V
required for the driver and control circuits by the ratio
(Duty Factor)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTV
mately 3mA of V
loss from 10% or more (if the driver was powered directly
from V
3) I
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
the average output current flows through L and R
but is “chopped” between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approxi-
mately the same R
MOSFET can simply be summed with the resistances of L,
R
R
total resistance is 25m . This results in losses ranging
from 2% to 8% as the output current increases from 3A to
15A per output stage for a 5V output, or a 3% to 12% loss
per output stage for a 3.3V output. Efficiency varies as the
inverse square of V
and output power level. The combined effects of increas-
ingly lower output voltages and higher currents required
by high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!
4) Transition losses apply only to the topside MOSFET(s),
and only when operating at high input voltages (typically
20V or greater). Transition losses can be estimated from:
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses in the
design of a system. The internal battery and input fuse
resistance losses can be minimized by making sure that
C
switching frequency. A 25W supply will typically require a
16
IN
SENSE
DS(ON)
Transition Loss = (1.7) V
2
has adequate charge storage and a very low ESR at the
R losses are predicted from the DC resistances of the
IN
and ESR to obtain I
=10m , R
) to only a few percent.
CC
IN
power through the EXTV
L
OUT
current. This reduces the mid-current
U
=10m , and R
DS(ON)
for the same external components
U
2
, then the resistance of one
CC
IN
R losses. For example, if each
2
current results in approxi-
I
O(MAX)
SENSE
W
C
RSS
=5m , then the
CC
f
switch input
U
IN
current
SENSE
,
minimum of 20 F to 40 F of capacitance having a maxi-
mum of 10m to 20m of ESR. The LTC1929 2-phase
architecture typically halves this input capacitance re-
quirement over competing solutions. Other losses includ-
ing Schottky conduction losses during dead-time and
inductor core losses generally account for less than 2%
total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, V
amount equal to I
series resistance of C
discharge C
forces the regulator to adapt to the current change and
return V
time V
ringing, which would indicate a stability problem. The
availability of the I
control loop behavior but also provides a DC coupled and
AC filtered closed loop response test point. The DC step,
rise time, and settling at this test point truly reflects the
closed loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at the pin. The I
shown in the Figure 1 circuit will provide an adequate
starting point for most applications.
The I
loop compensation. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to maximize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon because the various types and values determine the
loop feedback factor gain and phase. An output current
pulse of 20% to 80% of full-load current having a rise time
of <2 s will produce output voltage and I
TH
OUT
OUT
series R
can be monitored for excessive overshoot or
OUT
to its steady-state value. During this recovery
generating the feedback error signal that
C
-C
TH
LOAD
C
OUT
pin not only allows optimization of
filter sets the dominant pole-zero
(ESR), where ESR is the effective
( I
LOAD
TH
) also begins to charge or
external components
OUT
TH
pin waveforms
shifts by an