LT1764A LINER [Linear Technology], LT1764A Datasheet - Page 7

• Manufacturer Part Number: LT1764A
• Description: 1.1A, Low Noise, Low Dropout Linear Regulator
• Manufacturer: LINER [Linear Technology]

TYPICAL PERFORMANCE CHARACTERISTICS
PIN FUNCTIONS
OUT (Pins 1, 2 / 1, 2 / 4 / 4): Output. This pin supplies
power to the load. Use a minimum output capacitor of
10μF to prevent oscillations. Large load transient applica-
tions require larger output capacitors to limit peak volt-
age transients. See the Applications Information section
for more information on output capacitance and reverse
output characteristics.
ADJ (Pins 3 / 3 / 5 / 5): Adjust. This pin is the input to the
error amplifi er. It has a typical bias current of 1.3μA that
fl ows into the pin. The ADJ pin voltage is 1.20V referenced
to ground.
GND (Pins 4, 5 / 4, 5 / 3 / 3): Ground. For the adjustable
LT1965, connect the bottom of the resistor divider, setting
output voltage, directly to GND for optimum regulation.
⎯ S ⎯ H ⎯ D ⎯ N (Pin 6 / 6 / 1 / 1): Shutdown. Pulling the ⎯ S ⎯ H ⎯ D ⎯ N pin
low puts the LT1965 into a low power state and turns the
output off. Drive the ⎯ S ⎯ H ⎯ D ⎯ N pin with either logic or an open
collector/drain with a pull-up resistor. The resistor sup-
plies the pull-up current to the open collector/drain logic,
normally several microamperes and the ⎯ S ⎯ H ⎯ D ⎯ N pin current,
typically less than 6μA. If unused, connect the ⎯ S ⎯ H ⎯ D ⎯ N pin
to V
if the ⎯ S ⎯ H ⎯ D ⎯ N pin is not connected. The ⎯ S ⎯ H ⎯ D ⎯ N pin cannot
IN
. The LT1965 will be in its low power shutdown state
–100
100
–50
0.5
1.5
1.0
0.0
50
0
Transient Response
0
V
OUT
10
= 3.3V
20
(DFN/MSOP/DD-PAK/TO-220)
30
TIME (μs)
40
V
C
C
IN
IN
OUT
= 4.3V
= 10μF CERAMIC
50
= 10μF CERAMIC
60
70
1965 G25
80
be driven below GND unless it is tied to the IN pin. If the
⎯ S ⎯ H ⎯ D ⎯ N pin is driven below GND while IN is powered, the
output will turn on. ⎯ S ⎯ H ⎯ D ⎯ N pin logic cannot be referenced
to a negative supply rail.
IN (Pins 7, 8 / 7, 8 / 2 / 2): Input. This pin supplies power
to the device. The LT1965 requires a bypass capacitor at IN
if located more than six inches from the main input fi lter
capacitor. Include a bypass capacitor in battery-powered
circuits as a battery’s output impedance generally rises
with frequency. A bypass capacitor in the range of 1μF to
10μF suffi ces. The LT1965’s design withstands reverse
voltages on the IN pin with respect to ground and the
OUT pin. In the case of a reversed input, which occurs if
a battery is plugged in backwards, the LT1965 behaves
as if a diode is in series with its input. No reverse current
fl ows into the LT1965 and no reverse voltage appears at
the load. The device protects itself and the load.
Exposed Pad (Pin 9 / 9, DFN and MSOP Packages Only):
Ground. Tie this pin directly to Pins 4 and 5 and the PCB
ground. This pin provides enhanced thermal performance
with its connection to the PCB ground. See the Applica-
tions Information section for thermal considerations and
calculating junction temperature.
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
⎯ S ⎯ H ⎯ D ⎯ N Transient Response
V
C
R
IN
OUT
L
10
= 2.5k, I
= 3.3V
= 10μF CERAMIC
SHDN
20
L
30
= 1mA FOR V
OUTPUT
40
TIME (μs)
50
60
OUT
70
= 2.5V
80
90
1965 G26
100
LT1965
7
1965f