LTC2259-16 LINER [Linear Technology], LTC2259-16 Datasheet - Page 11

• Manufacturer Part Number: LTC2259-16
• Description: 16-Bit, 80Msps Ultralow Power 1.8V ADC
• Manufacturer: LINER [Linear Technology]

PIN FUNCTIONS
PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT
MODES
A
A
GND (Pin 3, Exposed Pad Pin 41): ADC Power Ground.
REFH (Pins 4, 5): ADC High Reference. Bypass to Pins
6, 7 with a 2.2μF ceramic capacitor and to ground with a
0.1μF ceramic capacitor.
REFL (Pins 6, 7): ADC Low Reference. Bypass to Pins
4, 5 with a 2.2μF ceramic capacitor and to ground with a
0.1μF ceramic capacitor.
PAR/SER (Pin 8): Programming Mode Selection Pin. Con-
nect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to V
parallel programming mode where CS, SCK, SDI become
parallel logic inputs that control a reduced set of the A/D
operating modes. PAR/SER should be connected directly
to ground or the V
logic signal.
V
to ground with 0.1μF ceramic capacitors. Pins 9 and 10
can share a bypass capacitor.
ENC
rising edge.
ENC
starts on the falling edge.
CS (Pin 13): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When
CS is low, SCK is enabled for shifting data on SDI into
the mode control registers. In the parallel programming
mode (PAR/SER = V
stabilizer. When CS is low, the clock duty cycle stabilizer is
turned off. When CS is high, the clock duty cycle stabilizer
is turned on. CS can be driven with 1.8V to 3.3V logic.
IN
IN
DD
+
–
+
–
(Pins 9, 10, 40): 1.8V Analog Power Supply. Bypass
(Pin 1): Positive Differential Analog Input.
(Pin 2): Negative Differential Analog Input.
(Pin 11): Encode Input. Conversion starts on the
(Pin 12): Encode Complement Input. Conversion
DD
DD
of the part and not be driven by a
), CS controls the clock duty cycle
DD
to enable the
SCK (Pin 14): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = V
digital output mode. When SCK is low, the full-rate CMOS
output mode is enabled. When SCK is high, the double-
data rate LVDS output mode (with 3.5mA output current)
is enabled. SCK can be driven with 1.8V to 3.3V logic.
SDI (Pin 15): In serial programming mode, (PAR/SER =
0V), SDI is the serial interface data input. Data on SDI is
clocked into the mode control registers on the rising edge
of SCK. In the parallel programming mode (PAR/SER =
V
is low, the part operates normally. When SDI is high, the
part enters sleep mode. SDI can be driven with 1.8V to
3.3V logic.
SDO (Pin 16): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control registers
and can be latched on the falling edge of SCK. SDO is an
open-drain NMOS output that requires an external 2k
pull-up resistor to 1.8V-3.3V. If read back from the mode
control registers is not needed, the pull-up resistor is not
necessary and SDO can be left unconnected. In the parallel
programming mode (PAR/SER = V
and should not be connected.
OGND (Pin 25): Output Driver Ground.
OV
with a 0.1μF ceramic capacitor.
V
Equal to V
mode of the analog inputs. Bypass to ground with a 0.1μF
ceramic capacitor.
V
with a 1μF ceramic capacitor, nominally 1.25V.
SENSE (Pin 39): Reference Programming Pin. Connecting
SENSE to V
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 • V
DD
CM
REF
DD
), SDI can be used to power down the part. When SDI
(Pin 38): Reference Voltage Output. Bypass to ground
(Pin 37): Common Mode Bias Output, Nominally
(Pin 26): Output Driver Supply. Bypass to ground
DD
DD
/2. V
selects the internal reference and a ±1V input
CM
should be used to bias the common
SENSE
.
LTC2259-16
DD
DD
), SCK controls the
), SDO is not used
11
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