LTC2351-12 LINER [Linear Technology], LTC2351-12 Datasheet
LTC2351-12
Related parts for LTC2351-12
LTC2351-12 Summary of contents
Page 1
... QFN package. A SLEEP shutdown mode further reduces power consumption to 12µW. The combination of low power and tiny package makes the LTC2351-12 suitable for portable applications. The LTC2351-12 contains six separate differential inputs that are sampled simultaneously on the rising edge of the CONV signal ...
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... LTC2351- BSOLUTE (Notes 1, 2) Supply Voltage ( .............................. Analog and V Input Voltages REF (Note 3) ................................... – 0. Digital Input Voltages .................. – 0. Digital Output Voltage .................. – 0. Power Dissipation .............................................. 100mW Operation Temperature Range LTC2351C-12 .......................................... 0°C to 70°C LTC2351I-12 ...................................... – 40°C to 85°C Storage Temperature Range ................. – ...
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... 3V – 200µA DD OUT V = 2.7V 160µA DD OUT V = 2.7V 1.6mA DD OUT and V OUT 0V OUT OUT DD LTC2351-12 MIN TYP MAX ● ● –80 –90 – – MIN TYP MAX 2.5 15 600 0 ...
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... LTC2351- POWER REQUIRE E TS range, otherwise specifications are at T SYMBOL PARAMETER Supply Voltage Supply Current Power Dissipation CHARACTERISTICS range, otherwise specifications are SYMBOL PARAMETER f Maximum Sampling Frequency per Channel SAMPLE(MAX) (Conversion Rate) t Minimum Sampling Period (Conversion + Acquisiton Period) ...
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... OUTPUT CODE LTC2351- 3V 25° THD, 2nd and 3rd vs Input Frequency –50 BIPOLAR SINGLE-ENDED –56 –62 THD –68 –74 2nd –80 –86 –92 –98 – ...
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... LTC2351- TYPICAL PERFOR A CE CHARACTERISTICS Full Scale Signal Response 3 0 –3 –6 –9 –12 –15 –18 –21 –24 –27 –30 10 100 FREQUENCY (MHz) Crosstalk vs Frequency 0 –20 –40 –60 –80 –100 –120 100 1k 10k 100k 1M FREQUENCY (Hz) 6 1000 235112 G10 10M 100M 1G ...
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... Care should be with a –2.5V to 0V, or taken to place the 0.1µF bypass capacitor as close to absolute DD Pin 24 as possible. Pin 24 must be tied to Pin 25. LTC2351-12 + operates – with 2.5V, absolute DD – operates fully + with a – ...
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... LTC2351- CTIO S V (Pin 25): 3V Positive Digital Supply. This pin supplies the logic section. Bypass to DGND pin and solid analog ground plane with a 10µF ceramic capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). Keep in mind that internal digital output signal currents flow through this pin. Care should be taken to place the 0.1µ ...
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... MUX 12-BIT LATCH 2 1.5Msps 12-BIT ADC 12-BIT LATCH 3 12-BIT LATCH 4 12-BIT LATCH 5 TIMING LOGIC 2.5V REFERENCE GND V BIP SEL2 SEL1 REF 10µF LTC2351- THREE- STATE 0.1µF SD0 SERIAL 1 OUTPUT OGND PORT 2 CONV 30 SCK 32 SEL0 DGND 31 235112 BD 235112f ...
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... LTC2351- DIAGRA S SCK 10 235112f ...
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... SCK CONV NAP SLEEP V REF NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS SCK SDO Nap Mode and Sleep Mode Waveforms t 1 SCK to SDO Delay SCK SDO V OL LTC2351- 1408 TD02 Hi-Z 1408 TD03 11 235112f ...
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... BIPOLAR, you can still read the first set of channels in the new mode, by inverting the MSB to read these channels in the mode that they were converted in. DRIVING THE ANALOG INPUT The differential analog inputs of the LTC2351-12 may be driven differentially single-ended input (i.e., the – CH0 input is grounded) ...
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... If slower op amps are used, more time for settling can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC2351-12 depends on the application. Generally, applications fall into two catego- ries: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical ...
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... Figure 1. RC Input Filter INPUT RANGE The analog inputs of the LTC2351-12 may be driven fully differentially with a single supply. Either input may swing 2.5V with BIP (Pin 29) Low, or ±1.25V with (BIP Pin 29) High. The 0V to 2.5V range is also ideally suited for single- ended input use with single supply applications ...
Page 15
... CMRR is typically better than –90dB Figure 4 shows the ideal input/output characteristics for the LTC2351-12 in unipolar mode (BIP = Low). The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, FS – 1.5LSB). The output code is straight binary with 1LSB = 2.5V/4096 = 610µ ...
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... SCK wake up the LTC2351-12 very quickly and CONV can start an accurate conversion within a clock cycle. Four rising edges at CONV, without any intervening rising edges at SCK, put the LTC2351-12 in Sleep mode and the power consumption drops from 16.5mW to 12µW. One or more rising edges at SCK wake up the LTC2351-12 for operation. The internal reference (V and settle with a 10µ ...
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... CONV rises, the third rising edge of SCK sends out up to six sets of 12 data bits, with the MSB sent first. A simple approach is to generate SCK to drive the LTC2351-12 first and then buffer this signal with the appropriate number of inverters to drive the serial clock input of the processor serial port ...
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... Figure 6 shows the recommended system ground connec- tions. All analog circuitry grounds should be terminated at the LTC2351-12 Exposed Pad. The ground return from the LTC2351-12 to the power supply should be low imped- ance for noise-free operation. The Exposed Pad of the 32- pin QFN package is also internally tied to the ground pads. ...
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... Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-169) 0.70 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC R = 0.05 0.75 ± 0.05 TYP 0.00 – 0.05 3.50 REF (4-SIDES) 0.200 REF LTC2351-12 BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.30 TYP R = 0.115 OR 0.35 × 45° CHAMFER TYP 31 32 0.40 ± 0. 3.45 ± 0.10 3.45 ± 0.10 (UH32) QFN 0406 REV D 0.25 ± ...
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... LTC2351-12 U TYPICAL APPLICATIO Low-Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level Shifting Circuit and Re-Timing Flip-Flop 50Ω RELATED PARTS PART NUMBER DESCRIPTION ADCs LTC1402 12-Bit, 2.2Msps Serial ADC LTC1403/LTC1403A 12-/14-Bit, 2.8Msps Serial ADC LTC1403-1/LTC1403A-1 12-/14-Bit, 2.8Msps Serial ADC LTC1405 ...