LTC2420I LINER [Linear Technology], LTC2420I Datasheet - Page 6

• Manufacturer Part Number: LTC2420I
• Description: 20-Bit uPower No Latency ADC in SO-8
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
LTC2420
Bit 21 (third output bit) is the conversion result sign indi-
cator (SIG). If V
bit is LOW. The sign bit changes state during the zero code.
Bit 20 (forth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0 V
normal input range, V
The function of these bits is summarized in Table 1.
Table 1. LTC2420 Status Bits
Input Range
V
0 < V
V
V
Bit 19 (fifth output bit) is the most significant bit (MSB).
Bits 19-0 are the 20-bit conversion result MSB first.
Bit 0 is the least significant bit (LSB).
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 2. Whenever CS is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 23 (EOC) can be captured on the first rising
6
IN
IN
IN
> V
= 0
< 0
IN
IN
REF
+
/0
V
–
REF
V
REF
SDO
SCK
CS
, this bit is LOW. If the input is outside the
IN
Bit 23
is >0, this bit is HIGH. If V
EOC
CONVERSION
U
0
0
0
0
IN
EOC = 1
> V
U
REF
Bit 22
DMY
or V
0
0
0
0
Figure 1. LTC2420 Compatible Timing with the LTC2400
IN
W
< 0, this bit is HIGH.
SLEEP
Bit 21
EOC = 0
SIG
1/0
1
1
0
IN
is <0, this
U
Bit 20
EXR
1
0
0
1
8
4 STATUS BITS 20 DATA BITS
edge of SCK. Bit 22 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 23rd SCK and may be latched on
the rising edge of the 24th SCK pulse. On the falling edge
of the 24th SCK pulse, SDO goes HIGH indicating a new
conversion cycle has been initiated. This bit serves as EOC
(Bit 23) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the V
the – 0.3V to (V
range, a conversion result is generated for any input value
from – 0.125 • V
greater than 1.125 • V
to the value corresponding to 1.125 • V
voltages below – 0.125 • V
clamped to the value corresponding to – 0.125 • V
Operation at Higher Data Output Rates
The LTC2420 typically operates with an internal oscillator
of 153.6kHz. This corresponds to a notch frequency of
60Hz and an output rate of 7.5 samples/second. The
internal oscillator is enabled if the F
(logic HIGH for a 50Hz notch). It is possible to drive the F
pin with an external oscillator for higher data output rates.
As shown in Figure 3, an external clock of 2.048MHz
applied to the F
with a data output rate of 100 samples/second.
Figure 4 shows the total unadjusted error (Offset Error +
Full-Scale Error + INL + DNL) as a function of the output
data rate with a 5V reference. The relationship between the
CONVERSION
DATA OUT
8
O
CC
8
pin results in a notch frequency of 800Hz
REF
+ 0.3V) absolute maximum operating
REF
to 1.125 • V
LAST 8 BITS ALWAYS 1
EOC = 1
, the conversion result is clamped
8 (OPTIONAL)
DATA OUTPUT
REF
IN
, the conversion result is
pin is maintained within
REF
. For input voltages
O
pin is logic LOW
2420 F01
REF
. For input
REF
.
O