LTC2607 LINER [Linear Technology], LTC2607 Datasheet - Page 17

• Manufacturer Part Number: LTC2607
• Manufacturer: LINER [Linear Technology]

operation
START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communica-
tion to a slave device by transmitting a START condition. A
START condition is generated by transitioning SDA from
high to low while SCL is high.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another I
Acknowledge
The acknowledge (ACK) signal is used for handshaking
between the master and the slave. An ACK generated by the
slave lets the master know that the latest byte of informa-
tion was properly received. The ACK related clock pulse is
generated by the master. The master releases the SDA line
(HIGH) during the ACK clock pulse. The slave-receiver must
pull down the SDA bus line during the ACK clock pulse
so that it remains a stable LOW during the HIGH period
of this clock pulse. The LTC2633 responds to a write by a
master in this manner but does not acknowledge a read
operation; in that case, SDA is retained HIGH during the
period of the ACK clock pulse.
Chip Address
The state of pin CA0 determines the slave address of the
part. This pin can be set to any one of three states: V
or float. This results in 3 selectable addresses for the part.
The slave address assignments is shown in Table 1.
Table 1. Slave Address Map
CA0
GND
FLOAT
V
GLOBAL ADDR
CC
2
C device.
A6
0
0
0
1
A5
0
0
0
1
A4
1
1
1
1
A3
0
0
0
0
A2
0
0
0
0
A1
0
0
1
1
CC
, GND
A0
0
1
0
1
In addition to the address selected by the address pin,
the part also responds to a global address. This address
allows a common write to all LTC2633 parts to be ac-
complished using one 3-byte write transaction on the I
bus. The global address, listed at the end of Tables 1, is a
7-bit hardwired address not selectable by CA0. If another
address is required, please consult the factory.
The maximum capacitive load allowed on the address pin
(CA0) is 10pF , as these pins are driven during address
detection to determine if they are floating.
Write Word Protocol
The master initiates communication with the LTC2633
with a START condition and a 7-bit slave address followed
by the write bit (W) = 0. The LTC2633 acknowledges by
pulling the SDA pin low at the 9th clock if the 7-bit slave
address matches the address of the part (set by CA0) or
the global address. The master then transmits three bytes
of data. The LTC2633 acknowledges each byte of data
by pulling the SDA line low at the 9th clock of each data
byte transmission. After receiving three complete bytes
of data, the LTC2633 executes the command specified in
the 24-bit input word.
If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2633 does not acknowledge the
extra bytes of data (SDA is high during the 9th clock).
LTC2633
17
2633fb
2
C