SAM3S ATMEL [ATMEL Corporation], SAM3S Datasheet - Page 26
SAM3S
Manufacturer Part Number
SAM3S
Description
ARM-based Flash MCU
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.SAM3S.pdf
(64 pages)
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6.3
6.4
6.5
26
Test Pin
NRST Pin
ERASE Pin
SAM3S Summary
The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming
mode of the SAM3S series. The TST pin integrates a permanent pull-down resistor of about 15
kΩ to GND, so that it can be left unconnected for normal operations. To enter fast programming
mode, see the Fast Flash Programming Interface (FFPI) section. For more on the manufacturing
and test mode, refer to the “Debug and Test” section of the product datasheet.
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low
to provide a reset signal to the external components or asserted low externally to reset the
microcontroller. It will reset the Core and the peripherals except the Backup region (RTC, RTT
and Supply Controller). There is no constraint on the length of the reset pulse and the reset con-
troller can guarantee a minimum pulse length. The NRST pin integrates a permanent pull-up
resistor to VDDIO of about 100 kΩ. By default, the NRST pin is configured as an input.
The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased
state (all bits read as logic level 1). It integrates a pull-down resistor of about 100 kΩ to GND, so
that it can be left unconnected for normal operations.
This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high
during less than 100 ms, it is not taken into account. The pin must be tied high during more than
220 ms to perform a Flash erase operation.
The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE
pin is not configured as a PIO pin. If the ERASE pin is used as a standard I/O, startup level of
this pin must be low to prevent unwanted erasing. Please refer to
nal Multiplexing on I/O Lines” on page
output, asserting the pin to low does not erase the Flash.
43. Also, if the ERASE pin is used as a standard I/O
Section 11.2 “Peripheral Sig-
6500CS–ATARM–24-Jan-11
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