LTC2754 LINER [Linear Technology], LTC2754 Datasheet - Page 16

• Manufacturer Part Number: LTC2754
• Description: Quad 12-/16-Bit SoftSpan IOUT DACs
• Manufacturer: LINER [Linear Technology]

LTC2754
System Offset and Reference Adjustments
The LTC2754 has individual offset- and gain- adjust pins
(V
DACs.
Many systems require compensation for overall system
offset. This may be an order of magnitude or more greater
than the offset of the LTC2754, which is so low as to be
dominated by external output amplifi er errors even when
using the most precise op amps.
The offset adjust pins V
unipolar offset or bipolar zero error. The offset-voltage
delta is inverted and attenuated such that a 5V control
voltage applied to V
(LTC2754-16) in any output range (assumes a 5V refer-
ence voltage at R
In voltage terms, the offset delta is attenuated by a factor
of 32, 64 or 128, depending on the output range. (These
functions hold regardless of reference voltage.)
ΔV
ΔV
spans]
ΔV
The gain error adjust pins GE
gain error or to compensate for reference errors. Nominal
adjustment range is ±512 LSB (LTC2754-16) for a volt-
age input range of ±V
input). The gain-error delta is non-inverting for positive
reference voltages.
Note that these pins compensate the gain by altering the
inverted reference voltage V
delta is inverted and attenuated by a factor of 128.
ΔV
The nominal input range of these pins is ±5V; other volt-
ages of up to ±15V may be used if needed. However, do
not use voltages divided down from power supplies; ref-
erence-quality, low-noise inputs are required to maintain
the performance of which the part is capable.
OPERATION
16
OSADJX
OS
OS
OS
REFX
= –(1/128)V
= –(1/32)V
= –(1/64)V
= –(1/128)GE
and GE
OSADJX
OSADJX
INX
ADJX
OSADJX
).
OSADJX
ADJX
, respectively) for each of its four
RINX
[±10V span]
[0V to 10V, ±5V, –2.5V to 7.5V
[0V to 5V, ±2.5V spans]
REFX
OSADJX
(i.e., ±5V for a 5V reference
produces ΔV
. In voltage terms, the V
ADJX
can be used to null
can be used to null
OS
= –512 LSB
REFX
The V
These pins should be driven with a Thevenin-equivalent
impedance of 10k or less to preserve the settling
performance of the LTC2754. They should be shorted to
GND if not used.
The GE
are intended for use with fi xed reference voltages only.
They should be shorted to GND if not used. If the reference
inverting resistors are not used for that channel, then
GE
Power-On Reset and Clear
When power is fi rst applied to the LTC2754, all DACs
power-up in unipolar 5V mode (S3 S2 S1 S0 = 0000). All
internal DAC registers are reset to 0 and the DAC outputs
initialize to zero volts.
If the part is confi gured for manual span operation, all four
DACs will be set into the pin-strapped range at the fi rst
Update command. This allows the user to simultaneously
update span and code for a smooth voltage transition into
the chosen output range.
When the CLR pin is taken low, a system clear results.
The DAC buffers are reset to 0 and the DAC outputs are
all reset to zero volts. The Input buffers are left intact, so
that any subsequent Update command (including the use
of LDAC) restores the addressed DACs to their respective
previous states.
If CLR is asserted during an instruction, i.e., when CS/LD
is low, the instruction is aborted. Integrity of the relevant
Input buffers is not guaranteed under these conditions,
therefore the contents should be checked using readback
or replaced.
The RFLAG pin is used as a fl ag to notify the system of a
loss of data integrity. The RFLAG output is asserted low
at power-up, system clear, or if the supply V
approximately 2V; and stays asserted until any valid Update
command is executed.
ADJX
OSADJX
ADJX
, R
COMX
pins have an input impedance of 2.56MΩ, and
pins have an input impedance of 1.28MΩ.
and R
INX
should all be shorted to REFX.
DD
dips below
2754f