LTC3554 LINER [Linear Technology], LTC3554 Datasheet - Page 30

• Manufacturer Part Number: LTC3554
• Description: Micropower USB Power Manager with Li-Ion Charger and Two Step-Down Regulators
• Manufacturer: LINER [Linear Technology]

LTC3554
Holding ON low through the one second power-down
period will not cause a power-up event at end of the one
second period. The ON pin must be brought high following
the power-down event and then go low again to establish
a valid power-up event.
UVLO Minimum Off-Time Timing (Low Battery)
Figure 11 assumes the battery is either missing or at a
voltage below the V
tion is running via external power (V
external supply causes V
threshold temporarily. This V
the pushbutton circuitry to transition from the PON state
to the PDN2 state. Upon entering the PDN2 state PGOOD
will go low and the bucks power down together.
30
OPERATION
STATE
PWR_ON1
PWR_ON2
ON (PB)
PBSTAT
PGOOD
BUCK1
BUCK2
V
BAT
BUS
Figure 11. UVLO Minimum Off-Time Timing
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
PON
OUT
PDN2
UVLO threshold, and the applica-
OUT
1s, BUCK1 POWERS UP
to drop below the V
OUT
BUCK2 POWERS UP
UVLO condition causes
230ms
PUP2
5s
5s
BUS
). A glitch on the
OUT
3554 TD05
PON
UVLO
In the typical case where the PWR_ON1 and PWR_ON2 pins
are driven by logic powered by the bucks, the PWR_ON1
and PWR_ON2 pins would also go low, as depicted in
Figure 11. If the external supply recovers after entering
the PDN2 state such that V
the LTC3554 will transition back into the PUP2 state once
the PDN2 one second delay is complete. Following the
state diagram, the transition from PDN2 to PUP2 in this
case actually occurs via a brief visit to the POFF state,
during which the state machine immediately recognizes
that valid external power is available and transitions into
the PUP2 state. Entering the PUP2 state will cause the
bucks to sequence up as described previously in the
power-up sections.
Not depicted here, but in the case where the PWR_ON
pins are driven by a supply other than the bucks, and
are able to remain high while both bucks are off in the
PDN2 state, then as per the state diagram in Figure 6,
once the one second PDN2 delay is over, the pushbutton
circuitry enters the POFF state. Provided at least one
PWR_ON pin is high, and V
pushbutton circuitry will transition directly into the PON
state, enabling the buck(s) corresponding to the asserted
PWR_ON pin(s).
Note: If V
will see this as a POR condition and will enter the PDN1
rather than the PDN2 state. One second later the part
will transition to the HR state. Under these conditions an
explicit power up event (such as a pushbutton press) may
be required to bring the LTC3554 out of hard reset.
Hard Reset Timing
HARD RESET provides an ultralow power-down state for
shipping or long term storage as well as a way to power
down the application in case of a software lockup. In the
case of software lockup, the user can hold the pushbutton
(ON low) for 5 seconds and a hard reset event (HRST) will
occur, placing the pushbutton circuitry in the power-down
(PDN1) state. At this point the bucks will be shut down
and PGOOD will go low. Following a one second power-
down period the pushbutton circuitry will enter the hard
reset state (HR).
OUT
drops too low (below about 1.9V ) the LTC3554
OUT
OUT
is no longer in UVLO, then
is no longer in UVLO, the
3554f