LTC3831 LINER [Linear Technology], LTC3831 Datasheet - Page 12

• Manufacturer Part Number: LTC3831
• Description: High Power Synchronous Switching Regulator Controller for DDR Memory Termination
• Manufacturer: LINER [Linear Technology]

LTC3831
APPLICATIO S I FOR ATIO
Q2. This circuit provides 2V
and V
of the Schottky diode. Ringing at the drain of Q2 can cause
transients above 2V
12V zener diode should be included from PV
to prevent transients from damaging the circuitry at PV
or the gate of Q1.
For applications with a lower V
pump circuit shown in Figure 7 can be used to provide 2V
and 3V
MOSFETs respectively. This circuit provides 3V
PV
the forward voltage of the Schottky diode. The circuit
requires the use of Schottky diodes to minimize forward
drop across the diodes at start-up. The tripling charge
pump circuit can rectify any ringing at the drain of Q2 and
provide more than 3V
be included from PV
from damaging the circuitry at PV
The charge pump capacitors for PV
BG pin goes high and the switch node is pulled low by Q2.
The BG on time becomes narrow when the LTC3831
operates at maximum duty cycle (95% typical) which can
occur if the input supply rises more slowly than the soft-
start capacitor or the input voltage droops during load
transients. If the BG on time gets so narrow that the switch
node fails to pull completely to ground, the charge pump
voltage may collapse or fail to start causing excessive
dissipation in external MOSFET Q1. This is most likely with
low V
with large external MOSFETs that slow the BG and switch
node slew rates.
The LTC3831 overcomes this problem by sensing the
PV
above V
by clamping the COMP pin at 1.8V (Q
Diagram). This increases the BG on time and allows the
charge pump capacitors to be refreshed.
12
CC1
CC1
IN
CC
while Q1 is ON and 2V
voltage when TG is high. If PV
– V
IN
CC
voltages and high switching frequencies, coupled
, the maximum TG duty cycle is reduced to 70%
F
gate drive for the external top and bottom
while Q1 is OFF where V
U
IN
IN
CC1
at PV
at PV
to PGND to prevent transients
U
IN
CC1
CC1
IN
– V
IN
; if V
– 2V
; a 12V zener diode should
F
supply, a tripling charge
to PV
CC1
F
W
IN
F
is the forward voltage
CC1
to PV
CC1
is higher than 7V, a
or the gate of Q1.
CC1
refresh when the
is less than 2.5V
C
CC2
while Q1 is ON
in the Block
CC1
where V
U
IN
to PGND
– 3V
F
CC1
F
to
IN
is
For applications using an external supply to power PV
this supply must also be higher than V
to ensure normal operation.
Connecting the Ratiometric Reference Input
The LTC3831 derives its ratiometric reference, V
using an internal resistor divider. The top and bottom of
the resistor divider is connected to the R
respectively. This permits the output voltage to track at a
ratio of the differential voltage at R
The LTC3831 can operate with a minimum V
maximum V
GND, this gives a V
3.5V). If V
increase the V
In a typical DDR memory termination application as shown
in Figure 1, R
the interface, and R
connected to the FB pin, so V
If a ratio greater than 0.5 is desired, it can be achieved
using an external resistor divider connected to V
pin. Figure 8 shows an application that generates a V
0.6 • V
10 F
D
12V
1N5242
Z
DDQ
LTC3831
PV
R
.
1N5817
+
CC2
FB
+
is higher than the permitted input voltage,
CC
is connected to V
Figure 7. Tripling Charge Pump
of (V
voltage to raise the input range.
PV
1N5817
CC1
R
–
CC
TG
BG
+
to GND. The output voltage V
input range of 2.2V to (2 • V
– 1.75V). With R
0.1 F
TT
DDQ
1N5817
= 0.5 • V
0.1 F
, the supply voltage of
+
V
and R
IN
Q1
Q2
CC
DDQ
by at least 2.5V
–
+
L
–
FB
O
connected to
.
and R
.
of 1.1V and
+
TT
and FB
3831 F07
–
C
OUT
TT
pins
CC
TT
CC1
REF
3831f
V
OUT
of
is
–
,
,