LTC3836 LINER [Linear Technology], LTC3836 Datasheet - Page 19

• Manufacturer Part Number: LTC3836
• Description: Dual 2-Phase, No RSENSETM Low VIN Synchronous Controller
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
For coincident tracking,
where V
of V
V
tracking function is desired, then the TRACK/SS2 pin may
be tied to a capacitor to ground, which sets the ramp time
to fi nal regulated output voltage.
Phase-Locked Loop and Frequency Synchronization
The LTC3836 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the main N-channel
MOSFET of controller 1 to be locked to the rising edge
of an external clock signal applied to the SYNC/FCB pin.
The turn-on of controller 2’s main N-channel MOSFET is
thus 180 degrees out-of-phase with the external clock.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
OUT2
t
SS2
OUT1
Figure 8. Relationship Between Oscillator Frequency
and Voltage at the PLLLPF Pin When Synchronizing to
an External Clock
when using the TRACK/SS2 pin for tracking. If no
= t
OUT1F
and V
1400
1200
1000
SS1
800
600
400
200
0
and V
0
•
OUT2
V
V
OUT2F
OUT1F
. V
0.5
OUT2F
PLLLPF PIN VOLTAGE (V)
OUT1
are the fi nal, regulated values
1
should always be greater than
1.5
2
3836 F08
2.4
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the external fi lter
network connected to the PLLLPF pin. The relationship
between the voltage on the PLLLPF pin and operating
frequency, when there is a clock signal applied to SYNC/
FCB, is shown in Figure 8 and specifi ed in the Electrical
Characteristics table. Note that the LTC3836 can only be
synchronized to an external clock whose frequency is within
range of the LTC3836’s internal VCO, which is nominally
200kHz to 1MHz. This is guaranteed, over temperature
and variations, to be between 300kHz and 750kHz. A
simplifi ed block diagram is shown in Figure 9.
If the external clock frequency is greater than the internal
oscillator’s frequency, f
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than f
the PLLLPF pin. If the external and internal frequencies
OSCILLATOR
EXTERNAL
OSC
Figure 9. Phase-Locked Loop Block Diagram
, current is sunk continuously, pulling down
SYNC/
FCB
FREQUENCY
DETECTOR
DIGITAL
PHASE/
OSC
, then current is sourced con-
2.4V
LTC3836
PLLLPF
R
LP
OSCILLATOR
19
3836 F09
C
3836fa
LP