SC16C2552 Philips Semiconductors, SC16C2552 Datasheet
SC16C2552
Available stocks
Related parts for SC16C2552
SC16C2552 Summary of contents
Page 1
... An internal loop-back capability allows on-board diagnostics. Independent programmable baud rate generators are provided to select transmit and receive baud rates. The SC16C2552 operates 3.3 V and 2.5 V, and the Industrial temperature range, and is available in a plastic PLCC44 package. 2. Features Industrial temperature range ( + ...
Page 2
... RESET A0–A2 REGISTER CS SELECT CHSEL LOGIC INTA, INTB INTERRUPT TXRDYA, TXRDYB CONTROL RXRDYA, RXRDYB LOGIC Fig 1. SC16C2552 block diagram. 9397 750 11636 Product data Dual UART with 16-byte transmit and receive FIFOs TRANSMIT TRANSMIT FIFO REGISTERS REGISTER RECEIVE RECEIVE FIFO REGISTERS ...
Page 3
... Chip Select (Active-LOW). This function is selects channel ‘A’ or ‘B’, in accordance with the logical state of the CHSEL pin. This allows data to be transferred between the user CPU and the SC16C2552, or the SC16C2552 and the CPU for a channel selected by CHSEL. MF[0] overrides CHSEL while in the write cycle mode, allowing the user to write both channel registers simultaneously with one write cycle ...
Page 4
... Read strobe (Active-LOW). A logic 0 transition on this pin will load the contents of an internal register defined by address bits A0-A2 onto the SC16C2552 data bus (D0-D7) for access by external CPU. Write strobe (Active-LOW). A logic 0 transition on this pin will transfer the contents of the data bus (D0-D7) from the external CPU to an internal register that is defi ...
Page 5
... RX input pin is disabled and TX data is connected to the UART RX input, internally. Transmit data A, B. These outputs are associated with individual serial transmit channel data from the SC16C2552. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the TX output pin is disabled and TX data is internally connected to the UART RX input. Rev. 03 — ...
Page 6
... The FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The SC16C2552 is capable of operation to 1.5 Mbits/s with a 24 MHz. With a crystal or external clock input of 7.3728 MHz, the user can select data rates up to 460 ...
Page 7
... Philips Semiconductors 6.2 Internal registers The SC16C2552 provides two sets of internal registers (A and B) consisting of 12 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status ...
Page 8
... TX/RX channel control. The programmable Baud Rate Generator is capable of accepting an input clock MHz, as required for supporting a 5 Mbits/s data rate. The SC16C2552 can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins. Alternatively, an external ...
Page 9
... Rev. 03 — 20 June 2003 SC16C2552 1 1.8432 MHz 002aaa169 DLM DLL program value program value (HEX) (HEX ...
Page 10
... Mode 1), the user takes the advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the receive trigger level and the transmit FIFO. In this mode, the SC16C2552 sets the interrupt output pin when characters in the transmit FIFO is below 16, or the characters in the receive FIFOs are above the receive trigger level ...
Page 11
... FIFO SHIFT REGISTERS REGISTER MODEM CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 Rev. 03 — 20 June 2003 SC16C2552 TXA, TXB MCR[ RXA, RXB RTSA, RTSB DSRA, DSRB DTRA, DTRB CTSA, CTSB OP1A, OP1B RIA, RIB OP2A, OP2B CDA, CDB 002aaa126 © ...
Page 12
... The Baud Rate register and AFR register sets are accessible only when logic 0 and LCR[ logic 1 for the register set (A/B) being accessed. 9397 750 11636 Product data Dual UART with 16-byte transmit and receive FIFOs details the assigned bit functions for the SC16C2552 internal registers. The Bit 7 Bit 6 Bit 5 Bit 4 ...
Page 13
... The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a Receive Serial Shift Register (RSR). Receive data is removed from the SC16C2552 and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16 clock rate ...
Page 14
... ISR register loading the THR with new data characters. 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C2552 in the FIFO polled mode of operation. In this mode, interrupts are not generated and the user must poll the LSR register for TX and/or RX data status ...
Page 15
... Logic 0 = Set DMA mode ‘0’ (normal default condition). Logic 1 = Set DMA mode ‘1’ Transmit operation in mode ‘0’: When the SC16C2552 is in the 16C450 mode (FIFOs disabled; FCR[0] = logic the FIFO mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no characters in the transmit FIFO or transmit holding register, the TXRDY pin will be a logic 0 ...
Page 16
... FIFO is completely full. It will be a logic 0 if one or more FIFO locations are empty. Receive operation in mode ‘1’: When the SC16C2552 is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached Receive Time-Out has occurred, the RXRDY signal at the MF pin will logic 0 ...
Page 17
... Philips Semiconductors 7.4 Interrupt Status Register (ISR) The SC16C2552 provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
Page 18
... LCR[2] stop bit length Word length Stop bit length (bit times LCR[1-0] word length LCR[0] Word length Rev. 03 — 20 June 2003 SC16C2552 Table 13). Table 14). Table 15). © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 19
... MCR[4] Loop-back. Enable the local loop-back mode (diagnostics). In this mode the transmitter output TX and the receiver input RX, CTS, DSR, CD, and RI are disconnected from the SC16C2552 I/O pins. Internally the modem data and control pins are connected into a loop-back data configuration (see and transmitter interrupts remain fully operational. The Modem Control Interrupts are also operational, but the interrupts’ ...
Page 20
... Philips Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C2552 and the CPU. Table 17: Bit 9397 750 11636 Product data Dual UART with 16-byte transmit and receive FIFOs Line Status Register bits description ...
Page 21
... A modem Status Interrupt will be generated. [1] MSR[2] RI Logic change (normal default condition). Logic 1 = The RI input to the SC16C2552 has changed from a logic logic 1. A modem Status Interrupt will be generated. [1] MSR[1] DSR Logic DSR change (normal default condition). ...
Page 22
... Philips Semiconductors 7.9 Scratchpad Register (SPR) The SC16C2552 provides a temporary data register to store 8 bits of user information. 7.10 Alternate Function Register (AFR) This is a read/write register used to select specific modes of MF operation and to allow both UART register’s sets to be written concurrently. Table 19: ...
Page 23
... Philips Semiconductors 7.11 SC16C2552 external reset conditions Table 21: Register IER ISR LCR MCR LSR MSR FCR AFR Table 22: Output TXA, TXB OP2A, OP2B RTSA, RTSB DTRA, DTRB INTA, INTB TXRDYA, TXRDYB 8. Limiting values Table 23: In accordance with the Absolute Maximum Rating System (IEC 60134). ...
Page 24
... 0.4 OL (databus 1 0.4 OL (other outputs (databus (other outputs 800 A 1. (data bus 400 A 1. (other outputs MHz - 3 Rev. 03 — 20 June 2003 SC16C2552 3.3 V 5.0 V Unit Min Max Min Max 0.3 0.6 0.5 0.6 V 2 0.3 0.8 0.5 0.8 V 2 ...
Page 25
... Rev. 03 — 20 June 2003 SC16C2552 3.3 V 5.0 V Unit Max Min Max - MHz - ...
Page 26
... Dual UART with 16-byte transmit and receive FIFOs t 6h VALID ADDRESS t 13h ACTIVE t 15d t 13w ACTIVE t 16h t 16s DATA t 6h VALID ADDRESS t 7h ACTIVE ACTIVE t 12h t 12d DATA Rev. 03 — 20 June 2003 SC16C2552 002aaa128 002aaa127 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 27
... Dual UART with 16-byte transmit and receive FIFOs t 17d CHANGE OF STATE CHANGE OF STATE t 18d ACTIVE t ACTIVE Rev. 03 — 20 June 2003 SC16C2552 CHANGE OF STATE t 18d ACTIVE ACTIVE 19d ACTIVE ACTIVE t 18d CHANGE OF STATE © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 002aaa352 002aaa112 ...
Page 28
... Product data Dual UART with 16-byte transmit and receive FIFOs DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS 16 BAUD RATE CLOCK Rev. 03 — 20 June 2003 SC16C2552 NEXT DATA PARITY STOP START BIT BIT BIT 20d ACTIVE t ...
Page 29
... Product data Dual UART with 16-byte transmit and receive FIFOs DATA BITS (5– DATA BITS (5– Rev. 03 — 20 June 2003 SC16C2552 NEXT DATA PARITY STOP START BIT BIT BIT 25d ACTIVE DATA READY t 26d ...
Page 30
... DATA BITS (5– DATA BITS 6 DATA BITS 7 DATA BITS ACTIVE TX READY t 22d 16 BAUD RATE CLOCK Rev. 03 — 20 June 2003 SC16C2552 NEXT DATA PARITY STOP START BIT BIT BIT 24d ACTIVE 002aaa116 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 31
... Philips Semiconductors Fig 13. Transmit ready timing in non-FIFO mode. 9397 750 11636 Product data Dual UART with 16-byte transmit and receive FIFOs Rev. 03 — 20 June 2003 SC16C2552 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 32
... Dual UART with 16-byte transmit and receive FIFOs DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS t 28d FIFO FULL Rev. 03 — 20 June 2003 SC16C2552 PARITY STOP BIT BIT D6 D7 002aaa346 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 33
... 16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07 0.656 0.656 0.63 0.63 0.695 0.695 0.048 0.05 0.650 0.650 0.59 0.59 0.685 0.685 0.042 REFERENCES JEDEC JEITA MS-018 EDR-7319 Rev. 03 — 20 June 2003 SC16C2552 SOT187 detail X (1) ( max. max. 1.44 0.18 0.18 0.1 2.16 2.16 1. ...
Page 34
... Product data Dual UART with 16-byte transmit and receive FIFOs 2.5 mm thick/large packages. Rev. 03 — 20 June 2003 SC16C2552 3 350 mm so called 3 so called small/thin packages. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 35
... Suitability of surface mount IC packages for wave and reflow soldering methods [1] [3] , [5] , SO, SOJ Rev. 03 — 20 June 2003 SC16C2552 Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable ...
Page 36
... Product data (9397 750 08936). ECN 853-2375 28891 of 10 September 2002. 9397 750 11636 Product data Dual UART with 16-byte transmit and receive FIFOs 10 C measured in the atmosphere of the reflow 9: changed capacitors’ values and Rev. 03 — 20 June 2003 SC16C2552 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 37
... Rev. 03 — 20 June 2003 SC16C2552 Fax: + 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 38
... Scratchpad Register (SPR 7.10 Alternate Function Register (AFR 7.11 SC16C2552 external reset conditions . . . . . . 23 © Koninklijke Philips Electronics N.V. 2003. Printed in the U.S.A All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice ...