AD724 Analog Devices, AD724 Datasheet - Page 14

• Manufacturer Part Number: AD724
• Description: RGB to NTSC/PAL Encoder
• Manufacturer: Analog Devices

Flicker is a fundamental defect of all interlaced displays and is
caused by the alternating field characteristic of the interlace
technique. Consider a one pixel high black line that extends
horizontally across a white screen. This line will exist in only
one field and will be refreshed at a rate of 30 Hz (25 Hz for
PAL). During the time that the other field is being displayed the
line will not be displayed. The human eye is capable of detect-
ing this, and the display will be perceived to have a pulsating or
flickering black line. This effect is highly content-sensitive and
is most pronounced in applications where text and thin
horizontal lines are present. In applications such as CD video,
photography and animation, portions of objects naturally
occur in both odd and even fields and the effect of flicker is
imperceptible.
The second commonly used technique is to output an identical
odd and even field (Figure 19b). This ignores the data that natu-
rally occurs in one of the fields. In this case the same one pixel
high line mentioned above would appear as a two pixel high line
(one pixel high in both the odd and even field) or will not appear at
all if it is in the data that is ignored by the controller. Which of
these cases occurs is dependent on the placement of the line on
the screen. This technique provides a stable (i.e., nonflickering)
display for all applications, but small text can be difficult to read
and lines in drawings (or spreadsheets) can disappear. As above,
graphics and animation are not particularly affected although
some resolution is lost.
There are methods to dramatically reduce the effect of flicker and
maintain high resolution. The most common is to ensure that
display data never exists solely in a single line. This can be ac-
complished by averaging/weighting the contents of successive/
multiple noninterlaced lines prior to creating a true interlaced
output (Figure 19c). In a sense this provides an output that will
lie between the two extremes described above. The weight or
percentage of one line that appears in another, and the number
of lines used, are variables that must be considered in develop-
ing a system of this type. If this type of signal processing is per-
formed, it must be completed prior to the data being presented
to the AD724 for encoding.
Vertical Scaling
In addition to converting the computer generated image from
noninterlaced to interlaced format, it is also necessary to scale
the image down to fit into NTSC or PAL format. The most
common vertical lines/screen for VGA display are 480 and 600
lines. NTSC can accommodate approximately 400 visible lines/
frame (200 per field), PAL can accommodate 576 lines/frame
(288 per field). If scaling is not performed, portions of the
original image will not appear in the television display.
This line reduction can be performed by merely eliminating
every Nth (6th line in converting 480 lines to NSTC or every 25th
line in converting 600 lines to PAL). This risks generation of jagged
edges and jerky movement. It is best to combine the scaling with
the interpolation/averaging technique discussed above to ensure
that valuable data is not arbitrarily discarded in the scaling pro-
cess. Like the flicker reduction technique mentioned above, the
line reduction must be accomplished prior to the AD724 encod-
ing operation.
There is a new generation of VGA controllers on the market
specifically designed to utilize these techniques to provide a
crisp and stable display for both text and graphics oriented ap-
plications. In addition, these chips rescale the output from the
AD724
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computer to fit correctly on the screen of a television. A list of
known devices is available through Analog Devices’ Applica-
tions group, but the most complete and current information will
be available from the manufacturers of graphics controller ICs.
Synchronous vs. Asynchronous Operation
The source of RGB video and synchronization used as an input
to the AD724 in some systems is derived from the same clock
signal as used for the AD724 subcarrier input (FIN). These
systems are said to be operating synchronously. In systems
where two different clock sources are used for these signals, the
operation is called asynchronous.
The AD724 supports both synchronous and asynchronous
operation, but some minor differences might be noticed be-
tween them. These can be caused by some details of the inter-
nal circuitry of the AD724.
There is an attempt to process all of the video and synchroniza-
tion signals totally asynchronous with respect to the subcarrier
signal. This was achieved everywhere except for the sampled
delay line used in the luminance channel to time align the lumi-
nance and chrominance. This delay line uses a signal at eight
times the subcarrier frequency as its clock.
The phasing between the delay line clock and the luminance
signal (with inserted composite sync) will be constant during
synchronous operation, while the phasing will demonstrate a
periodic variation during asynchronous operation. The jitter of
the asynchronous video output will be slightly greater due to
these periodic phase variations.
NONINTERLACED
NONINTERLACED
NONINTERLACED
a. Conversion of Noninterlace to Interlace
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b. Line Doubled Conversion Technique
c. Line Averaging Technique
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Figure 19.
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ODD FIELD
ODD FIELD
ODD FIELD
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EVEN FIELD
EVEN FIELD
EVEN FIELD
REV. B