AD73322 Analog Devices, AD73322 Datasheet - Page 2

• Manufacturer Part Number: AD73322
• Description: Low Cost/ Low Power CMOS General-Purpose Dual Analog Front End
• Manufacturer: Analog Devices

Parameter
REFERENCE
INPUT AMPLIFIER
ANALOG GAIN TAP
ADC SPECIFICATIONS
DIGITAL GAIN TAP
AD73322–SPECIFICATIONS
REFCAP
REFOUT
Offset
Maximum Output Swing
Feedback Resistance
Feedback Capacitance
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Gain Accuracy
Settling Time
Delay
Maximum Input Range at VIN
Nominal Reference Level at VIN
Absolute Gain
Gain Tracking Error
Signal to (Noise + Distortion)
Total Harmonic Distortion
Intermodulation Distortion
Idle Channel Noise
Crosstalk
DC Offset
Power Supply Rejection
Group Delay
Input Resistance at PGA
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Delay
Settling Time
Absolute Voltage, VREFCAP
REFCAP TC
Typical Output Impedance
Absolute Voltage, V
Minimum Load Resistance
Maximum Load Capacitance
(0 dBm0)
PGA = 0 dB
PGA = 38 dB
PGA = 0 dB
PGA = 38 dB
PGA = 0 dB
PGA = 38 dB
4, 5
ADC-to-ADC
ADC-to-DAC
REFOUT
2, 4, 6
2, 3
Min
1.08
1.08
1
–0.5
–1.5
72
55
52
–30
1
AD73322A
(AVDD = +3 V
16.384 MHz, f
–100
Typ
1.2
50
130
1.2
1.578
50
100
+1
–1
5
1.0
0.5
1.578
–2.85
1.0954
–6.02
0.4
–0.7
78
78
57
56
–84
–70
–65
–71
–100
–70
+10
–65
25
20
+1
–1
16
25
100
1.0
1.0
0.1
–2–
Max
1.32
1.32
100
+1.2
+0.1
–73
–60
+45
SAMP
10%; DVDD = +3 V
= 64 kHz; T
dB
dB
Units
V
ppm/ C 0.1 F Capacitor Required from
V
k
pF
mV
V
pF
Bits
%
V p-p
dBm
V p-p
dBm
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dBm0
dB
mV
dB
k
Bits
s
s
s
s
s
A
= T
5VEN = 0
Refer to Figure 5
ADC Input Signal Level: 1.0 kHz, 0 dBm0
ADC1 Input Signal Level: 1.0 kHz, 0 dBm0
Test Conditions/Comments
REFCAP to AGND2
Unloaded
Max Output Swing = (1.578/1.2) VREFCAP
f
Gain Step Size = 0.0625
Output Unloaded
Tap Gain Change of –FS to +FS
5VEN = 0
Measured Differentially
Max Input = (1.578/1.2)
Measured Differentially
1.0 kHz, 0 dBm0
1.0 kHz, 0 dBm0
1.0 kHz, +3 dBm0 to –50 dBm0
300 Hz to 3400 Hz; f
300 Hz to 3400 Hz; f
0 Hz to f
300 Hz to 3400 Hz; f
300 Hz to 3400 Hz; f
300 Hz to 3400 Hz; f
PGA = 0 dB
PGA = 0 dB
DAC Input at Idle
ADC2 Input at Idle. Input Amplifiers Bypassed
Input Amplifiers Included in Input Channel
PGA = 0 dB
Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
Input Amplifiers Bypassed
Tested to 5 MSBs of Settings
Includes DAC Delay
Tap Gain Change from –FS to +FS; Includes
DAC Settling Time
C
MIN
= 32 kHz
to T
10%; DGND = AGND = 0 V, f
MAX
SAMP
, unless otherwise noted)
/2; f
SAMP
SAMP
SAMP
SAMP
SAMP
SAMP
= 64 kHz
= 64 kHz
= 8 kHz
= 64 kHz
= 64 kHz
= 64 kHz
VREFCAP
DMCLK
=
REV. B